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LM3S1918 Datasheet, PDF (10/632 Pages) Texas Instruments – Stellaris® LM3S1918 Microcontroller
Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 3-1.
Figure 4-1.
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Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
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Figure 11-5.
Figure 12-1.
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Figure 12-3.
Figure 13-1.
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Figure 13-5.
Figure 13-6.
Figure 13-7.
Stellaris LM3S1918 Microcontroller High-Level Block Diagram ............................... 39
CPU Block Diagram ............................................................................................. 48
TPIU Block Diagram ............................................................................................ 49
Cortex-M3 Register Set ........................................................................................ 51
Bit-Band Mapping ................................................................................................ 71
Data Storage ....................................................................................................... 72
Vector Table ........................................................................................................ 78
Exception Stack Frame ........................................................................................ 80
SRD Use Example ............................................................................................... 94
JTAG Module Block Diagram .............................................................................. 153
Test Access Port State Machine ......................................................................... 157
IDCODE Register Format ................................................................................... 163
BYPASS Register Format ................................................................................... 163
Boundary Scan Register Format ......................................................................... 164
Basic RST Configuration .................................................................................... 167
External Circuitry to Extend Power-On Reset ....................................................... 168
Reset Circuit Controlled by Switch ...................................................................... 168
Power Architecture ............................................................................................ 170
Main Clock Tree ................................................................................................ 173
Hibernation Module Block Diagram ..................................................................... 233
Clock Source Using Crystal ................................................................................ 235
Clock Source Using Dedicated Oscillator ............................................................. 236
Flash Block Diagram .......................................................................................... 253
GPIO Port Block Diagram ................................................................................... 286
GPIODATA Write Example ................................................................................. 287
GPIODATA Read Example ................................................................................. 287
GPTM Module Block Diagram ............................................................................ 328
16-Bit Input Edge Count Mode Example .............................................................. 333
16-Bit Input Edge Time Mode Example ............................................................... 334
16-Bit PWM Mode Example ................................................................................ 335
WDT Module Block Diagram .............................................................................. 365
ADC Module Block Diagram ............................................................................... 389
Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 393
Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 393
Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 394
Internal Temperature Sensor Characteristic ......................................................... 395
UART Module Block Diagram ............................................................................. 425
UART Character Frame ..................................................................................... 426
IrDA Data Modulation ......................................................................................... 428
SSI Module Block Diagram ................................................................................. 466
TI Synchronous Serial Frame Format (Single Transfer) ........................................ 469
TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 470
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 471
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 471
Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 472
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 473
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June 19, 2012
Texas Instruments-Production Data