DS90LV049Q_15 Datasheet, PDF (10/17 Pages) Texas Instruments – Automotive LVDS Dual Line Driver and Receiver Pair

DS90LV049Q
SNLS300D – MAY 2008 – REVISED APRIL 2013
www.ti.com
CABLES AND CONNECTORS, GENERAL COMMENTS
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100 Ω. They should not introduce major impedance discontinuities.
Balanced cables (for example, twisted pair) are usually better than unbalanced cables (ribbon cable, simple
coax.) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling
effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is
rejected by the receiver.
FAIL-SAFE FEATURE
An LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20 mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for floating receiver inputs.
The DS90LV049Q has two receivers, and if an application requires a single receiver, the unused receiver inputs
should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by
internal high value pull up and pull down current sources to set the output to a HIGH state. This internal circuitry
will ensure a HIGH, stable output state for open inputs.
External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pull up and pull down resistors should be in the 5 kΩ to 15 kΩ range to
minimize loading and waveform distortion to the driver. The common-mode bias point should be set to
approximately 1.2 V (less than 1.75 V) to be compatible with the internal circuitry.
For more information on failsafe biasing of LVDS interfaces, please refer to AN-1194 (SNLA051).
Pin No.
10, 11
6, 7
5, 8
2, 3
1, 4
14, 15
9, 16
12
13
Name
D_IN
D_OUT+
D_OUT−
R_IN+
R_IN-
R_OUT
EN, EN
V_DD
GND
PIN DESCRIPTIONS
Description
Driver input pins, LVCMOS levels. There is a pull-down current source present.
Non-inverting driver output pins, LVDS levels.
Inverting driver output pins, LVDS levels.
Non-inverting receiver input pins, LVDS levels. There is a pull-up current source present.
Inverting receiver input pins, LVDS levels. There is a pull-down current source present.
Receiver output pins, LVCMOS levels.
Enable and Disable pins. There are pull-down current sources present at both pins.
Power supply pin.
Ground pin.
10
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS90LV049Q