ADS8364_16 Datasheet, PDF (10/27 Pages) Texas Instruments – 250kSPS, 16-Bit, 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTERS

INTRODUCTION
The ADS8364 is a high-speed, low-power, 6-channel simul-
taneous sampling and converting, 16-bit ADC that operates
from a single +5V supply. The input channels are fully
differential with a typical common-mode rejection of 80dB.
The part contains six 4µs successive approximation ADCs,
six differential sample-and-hold amplifiers, an internal +2.5V
reference with REF_IN and REF_OUT pins and a high-speed
parallel interface. There are six analog inputs that are grouped
into three channel pairs (A, B, and C). There are six ADCs,
one for each input that can be sampled and converted
simultaneously, thus preserving the relative phase informa-
tion of the signals on both analog inputs. Each pair of
channels has a hold signal (HOLDA, HOLDB, and HOLDC)
to allow simultaneous sampling on each channel pair, on
four or on all six channels. The part accepts a differential
analog input voltage in the range of –V_REF to +V_REF, centered
on the common-mode voltage (see the Analog Input Section).
The part will also accept bipolar input ranges when a level shift
circuit is used at the front end (see Figure 6).
A conversion is initiated on the ADS8364 by bringing the
HOLDX pin LOW for a minimum of 20ns. HOLDX LOW
places the sample-and-hold amplifiers of the X channels in
the hold state simultaneously and the conversion process is
started on each channel. The EOC output will go LOW for
half a clock cycle when the conversion is latched into the
output register. The data can be read from the parallel output
bus following the conversion by bringing both RD and CS
LOW.
Conversion time for the ADS8364 is 3.2µs when a 5MHz
external clock is used. The corresponding acquisition time is
0.8µs. To achieve the maximum output data rate (250kSPS),
the read function can be performed during the next conver-
sion. Note: This mode of operation is described in more
detail in the Timing and Control section of this data sheet.
SAMPLE-AND-HOLD SECTION
The sample-and-hold amplifiers on the ADS8364 allow the
ADCs to accurately convert an input sine wave of full-scale
amplitude to 16-bit resolution. The input bandwidth of the
sample-and-hold is greater than the Nyquist rate (Nyquist
equals one-half of the sampling rate) of the ADC even when
the ADC is operated at its maximum throughput rate of
250kSPS. The typical small-signal bandwidth of the sample-
and-hold amplifiers is 300MHz.
Typical aperture delay time or the time it takes for the
ADS8364 to switch from the sample to the hold mode
following the negative edge of HOLDX signal is 5ns. The
average delta of repeated aperture delay values is typically
50ps (also known as aperture jitter). These specifications
reflect the ability of the ADS8364 to capture AC input signals
accurately at the exact same moment in time.
REFERENCE
Under normal operation, the REF_OUT (pin 61) can directly be
connected to the REF_IN pin (pin 62) to provide an internal
+2.5V reference to the ADS8364. The ADS8364 can
operate, however, with an external reference in the range of
1.5V to 2.6V, for a corresponding full-scale range of 3.0V to
5.2V, as long as the input does not exceed the AV_DD + 0.3V
value.
The reference of the ADS8364 is double-buffered. If the
internal reference is used to drive an external load, a buffer
is provided between the reference and the load applied to pin
61 (the internal reference can typically source 10µA of
current—load capacitance should be 0.1µF and 10µF to
minimize noise). If an external reference is used, the three-
second buffers provide isolation between the external refer-
ence and the CDACs. These buffers are also used to
recharge all of the capacitors of all CDACs during conver-
sion.
ANALOG INPUT
The analog input is bipolar and fully differential. There are two
general methods of driving the analog input of the ADS8364:
single-ended or differential, as shown in Figure 1 and
Figure 2. When the input is single-ended, the –IN input is held
at the common-mode voltage. The +IN input swings around
the same common voltage and the peak-to-peak amplitude is
the (common-mode + V_REF) and the (common-mode – V_REF).
The value of V_REF determines the range over which the
common-mode voltage may vary (see Figure 3).
–V_REF to +V_REF
peak-to-peak
Common
Voltage
ADS8364
Single-Ended Input
Common
Voltage
V_REF
peak-to-peak
V_REF
peak-to-peak
Differential Input
ADS8364
FIGURE 1. Methods of Driving the ADS8364 Single-Ended or
Differential.
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ADS8364
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