ADS7843 Datasheet, PDF (10/18 Pages) Burr-Brown (TI) – TOUCH SCREEN CONTROLLER

This is possible provided that each conversion completes
within 1.6ms of starting. Otherwise, the signal that has been
captured on the input sample-and-hold may droop enough to
affect the conversion result. Note that the ADS7843 is fully
powered while other serial communications are taking place
during a conversion.
Digital Timing
Figure 7 and Table VI provide detailed timing for the digital
interface of the ADS7843.
SYMBOL
DESCRIPTION
MIN
t_ACQ
Acquisition Time
1.5
t_DS
DIN Valid Prior to DCLK Rising 100
t_DH
DIN Hold After DCLK HIGH 10
t_DO
DCLK Falling to DOUT Valid
t_DV
CS Falling to DOUT Enabled
t_TR
CS Rising to DOUT Disabled
t_CSS CS Falling to First DCLK Rising 100
t_CSH
CS Rising to DCLK Ignored
0
t_CH
DCLK HIGH
200
t_CL
DCLK LOW
200
t_BD
DCLK Falling to BUSY Rising
t_BDV
CS Falling to BUSY Enabled
t_BTR
CS Rising to BUSY Disabled
TYP MAX UNITS
µs
ns
ns
200 ns
200 ns
200 ns
ns
ns
ns
ns
200 ns
200 ns
200 ns
TABLE VI. Timing Specifications (+V_CC = +2.7V and Above,
T_A = –40°C to +85°C, C_LOAD = 50pF).
Data Format
The ADS7843 output data is in Straight Binary format, as
shown in Figure 8. This figure shows the ideal output code for
the given input voltage and does not include the effects of
offset, gain, or noise.
11...111
11...110
11...101
FS = Full-Scale Voltage = V_REF(1)
1LSB = V_REF(1)/4096
1LSB
00...010
00...001
00...000
0V
FS – 1LSB
Input Voltage⁽²⁾ (V)
NOTES: (1) Reference voltage at converter: +REF – (–REF). See Figure 2.
(2) Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 2
FIGURE 8. Ideal Input Voltages and Output Codes.
8-Bit Conversion
The ADS7843 provides an 8-bit conversion mode that can be
used when faster throughput is needed and the digital result
is not as critical. By switching to the 8-bit mode, a conversion
is complete four clock cycles earlier. This could be used in
conjunction with serial interfaces that provide 12-bit transfers
or two conversions could be accomplished with three 8-bit
transfers. Not only does this shorten each conversion by four
bits (25% faster throughput), but each conversion can actu-
ally occur at a faster clock rate. This is because the internal
settling time of the ADS7843 is not as critical—settling to
better than 8 bits is all that is needed. The clock rate can be
as much as 50% faster. The faster clock rate and fewer clock
cycles combine to provide a 2x increase in conversion rate.
CS
DCLK
DIN
t_CSS
t_CH
t_DS
t_CL
t_BD
t_BD
t_DH
PD0
t_D0
t_CSH
t_BDV
t_BTR
BUSY
t_DV
DOUT
t_TR
11
10
FIGURE 7. Detailed Timing Diagram.
10
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ADS7843
SBAS090B