ADS7843-Q1 Datasheet, PDF (10/21 Pages) Texas Instruments – TOUCH SCREEN CONTROLLER

ADS7843-Q1
SBAS504A – MARCH 2011 – REVISED JULY 2012
www.ti.com
Figure 15. Simplified Diagram of Differential Reference (SER/DFR LOW, Y Switches Enabled, X+ is
Analog Input).
DIGITAL INTERFACE
Figure 16 shows the typical operation of the
ADS7843-Q1’s digital interface. This diagram
assumes that the source of the digital signals is a
microcontroller or digital signal processor with a basic
serial interface. Each communication between the
processor and the converter consists of eight clock
cycles. One complete conversion can be
accomplished with three serial communications, for a
total of 24 clock cycles on the DCLK input.
The first eight clock cycles are used to provide the
control byte via the DIN pin. When the converter has
enough information about the following conversion to
set the input multiplexer, switches, and reference
inputs appropriately, the converter enters the
acquisition (sample) mode and, if needed, the internal
switches are turned on. After three more clock cycles,
the control byte is complete and the converter enters
the conversion mode. At this point, the input sample-
and-hold goes into the hold mode and the internal
switches may turn off. The next 12th clock cycles
accomplish the actual A/D conversion. If the
conversion is ratiometric (SER/DFR LOW), the
internal switches are on during the conversion. A 13th
clock cycle is needed for the last bit of the conversion
result. Three more clock cycles are needed to
complete the last byte (DOUT will be LOW). These
will be ignored by the converter.
Figure 16. Conversion Timing, 24 Clocks per
Conversion, 8-bit Bus Interface. No DCLK Delay
Required with Dedicated Serial Port.
Control Byte
See Figure 16 for the placement and order of the
control bits within the control byte. Table 3 and
Table 4 give detailed information about these bits.
The first bit, the ‘S’ bit, must always be HIGH and
indicates the start of the control byte. The ADS7843-
Q1 will ignore inputs on the DIN pin until the start bit
is detected. The next three bits (A2-A0) select the
active input channel or channels of the input
multiplexer (see Table 1 and Table 2 and Figure 13).
The MODE bit determines the number of bits for each
conversion, either 12 bits (LOW) or 8 bits (HIGH).
The SER/DFR bit controls the reference mode: either
single-ended (HIGH) or differential (LOW). (The
differential mode is also referred to as the ratiometric
conversion mode.) In single-ended mode, the
converter’s reference voltage is always the difference
between the VREF and GND pins. In differential
mode, the reference voltage is the difference between
the currently enabled switches. See Table 1 and
Table 2 and Figure 13 through Figure 15 for more
information. The last two bits (PD1-PD0) select the
power-down mode as shown in Table 5. If both inputs
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