74SSTUB32868A Datasheet, PDF (10/25 Pages) Texas Instruments – 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST

74SSTUB32868A
SCAS846C – JULY 2007 – REVISED MARCH 2009.......................................................................................................................................................... www.ti.com
Parity Logic Diagram for Register-B Configuration (Positive Logic); C = 1
RESET ^M2
CLK ^L1
CLK ^M1
D1−D12,
D17−D20,
D22,
22
D24−D28
V_REF ^{A5, AB5}
D1−D12,
D17−D20, D22,
D24−D28
D
22
CLK Q
R _CE
D1−D12,
D17−D20, D22,
D24−D28
22
22
D1−D12,
D17−D20, D22,
D24−D28
Q1A−Q12A,
Q17A−Q20A,
22 _Q22A,
Q24A−Q28A
22 _{Q1B−Q12B,}
Q17B−Q20B,
Q22B,
Q24B−Q28B
PAR_IN ^L3
D
CLK Q
R
CE
Parity Generator
and
Error Check
M3
QERR
DCS0 ^N1
CSGEN ^L2
DCS1 ^P1
D
CLK Q
R
D
CLK Q
R
N2 _QCS0A
M7 _QCS0B
P2 _QCS1A
M8 _QCS1B
10
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