VSP3200_14 Datasheet, PDF (1/6 Pages) Texas Instruments – CCD SIGNAL PROCESSOR FOR SCANNER APPLICATIONS

Not Recommended For New Designs
VSP3200
VSP3200
VSP3210
www.ti.com
CCD SIGNAL PROCESSOR FOR
SCANNER APPLICATIONS
FEATURES
F INTEGRATED TRIPLE-CORRELATED
DOUBLE SAMPLER
F OPERATION MODE SELECTABLE:
1-Channel, 3-Channel CCD Mode, 8Msps
F PROGRAMMABLE GAIN AMPLIFIER:
0dB to +13dB
F SELECTABLE OUTPUT MODES:
Normal/Demultiplexed
F OFFSET CONTROL RANGE: ±500mV
F +3V, +5V Digital Output
F LOW POWER: 300mW (typ)
F LQFP-48 SURFACE-MOUNT PACKAGE
DESCRIPTION
The VSP3200 and VSP3210 are complete CCD image
processors that operate from single +5V supplies.
This complete image processor includes three Corre-
lated Double Samplers (CDSs) and Programmable
Gain Amplifiers (PGAs) to process CCD signals.
The VSP3200 is interface compatible with the
VSP3210, which is a 16-bit, one-chip product.
The VSP3210 is pin-to-pin compatible with VSP3100,
when in demultiplexed output mode.
The VSP3200 and VSP3210 can be operated from 0°C
to +85°C, and are available in LQFP-48 packages.
CLP
RINP
AGND
Clamp
GINP
Clamp
10
10-Bit
DAC
BINP
Clamp
Offset
Register
R
G
B
10
10-Bit
DAC
10
10-Bit
DAC
CK1 CK2
CDS
CDS
ADCCK
TP0
V_REF
PGA
Timing Generator
6
Reference
Circuit
PGA
6
MUX
16-Bit
A/D
Converter
Digital
Output
16 Control
CDS
PGA
Configuration
Register
6
8
VSP3200
Gain
Control
Register
R
G
B
6
3
Register
10
Port
CM
REFP
REFN
OE
V_DRV
B0-B15
(A0-A2, D0-D9)
P/S
WRT
RD
SCLK
SD
Copyright © 2000, Texas Instruments Incorporated
SBMS012A
Printed in U.S.A. November, 2000