TSB41LV03A_14 Datasheet, PDF (1/11 Pages) Texas Instruments – IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER

Not Recommended for New Designs
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TSB41LV03A
TSB41LV03AI
SLLA225 – JUNE 2006
IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER
FEATURES
• Fully Supports Provisions of IEEE 1394-1995
Standard for High Performance Serial Bus¹
and the P1394a Supplement
• Fully Interoperable With FireWire™ and
i.LINK™ Implementation of IEEE Std 1394
• Fully Compliant With OpenHCI Requirements
• Provides Three P1394a Fully Compliant Cable
Ports at 100/200/400 Megabits per Second
(Mbits/s)
• Full P1394a Support Includes: Connection
Debounce, Arbitrated Short Reset, Multispeed
Concatenation, Arbitration Acceleration,
Fly-By Concatenation, Port
Disable/Suspend/Resume
• Extended Resume Signaling for Compatibility
With Legacy DV Devices
• Power-Down Features to Conserve Energy in
Battery Powered Applications Include:
Automatic Device Power-Down During
Suspend, Device Power-Down Terminal, Link
Interface Disable via LPS, and Inactive Ports
Powered Down
• Ultralow-Power Sleep Mode
• Node Power Class Information Signaling for
System Power Management
• Cable Power Presence Monitoring
• Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
• Register Bits Give Software Control of
Contender Bit, Power Class bits, Link Active
Control Bit and P1394a Features
• Data Interface to Link-Layer Controller
Through 2/4/8 Parallel Lines at 49.152 MHz
• Interface to Link Layer Controller Supports
Low Cost TI Bus-Holder Isolation and
Optional Annex J Electrical Isolation
• Interoperable With Link-Layer Controllers
Using 3.3-V and 5-V Supplies
• Interoperable With Other Physical Layers
(PHYs) Using 3.3-V and 5-V Supplies
• Low Cost 24.576-MHz Crystal Provides
Transmit, Receive Data at 100/200/400
Mbits/s, and Link-Layer Controller Clock at
49.152 MHz
• Incoming Data Resynchronized to Local
Clock
• Logic Performs System Initialization and
Arbitration Functions
• Encode and Decode Functions Included for
Data–Strobe Bit Level Encoding
• Separate Cable Bias (TPBIAS) for Each Port
• Single 3.3-V Supply Operation
• Low Cost High Performance 80-Pin TQFP
(PFP) Thermally Enhanced Package
• Direct Drop-In Upgrade for TSB41LV03PFP
NOTE: Implements technology covered by one or more patents
of Apple Computer, Incorporated and SGS Thompson,
Limited.
DESCRIPTION
The TSB41LV03A provides the digital and analog transceiver functions needed to implement a three-port node
in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for
initialization and arbitration, and for packet reception and transmission. The TSB41LV03A is designed to
interface with a line layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV31,
TSB12LV41, TSB12LV42, or TSB12LV01A.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FireWire is a trademark of Apple Computer, Incorporated.
i.LINK is a trademark of Sony Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated