TPS7A89 Datasheet, PDF (1/7 Pages) Texas Instruments – LDO Voltage Regulator

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TPS7A89
SBVS280 – MARCH 2016
TPS7A89
Small, Dual 2-A, Low-Noise (3.8 μVRMS), LDO Voltage Regulator
1 Features
•1 Two Independent LDO Channels
• 4-mm × 4-mm, 20-Pin WQFN Package
• Low Output Noise: < 3.8 µV_RMS (10 Hz–100 kHz)
• Low Dropout: 250 mV (Typ) at 2 A
• Wide Input Voltage Range: 1.4 V to 6.5 V
• Wide Output Voltage Range: 0.8 V to 5.2 V
• High Power-Supply Ripple Rejection:
– 75 dB at DC
– 40 dB at 100 kHz
– 40 dB at 1 MHz
• 1.0% Accuracy Over Line, Load, and Temperature
• Excellent Load Transient Response
• Adjustable Start-Up In-Rush Control
• Selectable Soft-Start Charging Current
• Independent Open-Drain Power-Good (PG)
Outputs
• Stable with a 10-µF or Larger Ceramic Output
Capacitor
2 Applications
• High-Speed Analog Circuits:
– VCO, ADC, DAC, LVDS
• Imaging: CMOS Sensors, Video ASICs
• Test and Measurement
• Instrumentation, Medical, and Audio
• Digital Loads Auxiliary Rails: SerDes, FPGA, DSP
3 Description
The TPS7A89 is a dual, low-noise (3.8 µV_RMS), low-
dropout (LDO) voltage regulator capable of sourcing
2 A per channel with only 400 mV of maximum
dropout.
The TPS7A89 provides the flexibility of two
independent LDOs and approximately 60% smaller
solution size than two single-channel LDOs. Each
output is adjustable with external resistors from 0.8 V
to 5.2 V. The wide input-voltage range of the
TPS7A89 supports operation as low as 1.4 V and up
to 6.5 V.
With 1% output voltage accuracy (over line, load, and
temperature) and soft-start capabilities to reduce in-
rush current, the TPS7A89 is ideal for powering
sensitive analog low-voltage devices [such as
voltage-controlled oscillators (VCOs), analog-to-digital
converters (ADCs), digital-to-analog converters
(DACs), high-end processors, and field-
programmable gate arrays (FPGAs)].
The TPS7A89 is designed to power noise-sensitive
components such as those found in high-speed
communication, video, medical, or test and
measurement applications. The very low 3.8-µV_RMS
output noise and wideband PSRR (40 dB at 1 MHz)
minimizes phase noise and clock jitter. These
features maximize performance of clocking devices,
ADCs, and DACs.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS7A89
WQFN (20)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical Application Diagram
VIN1
EN1
VIN2
EN2
IN1
PG1
EN1
OUT1
TPS7A89
IN2
EN2
OUT2
PG2
EN VDD
ADC
ADS4xJBxx
ADC5xJxx
ADC12Jxxxx
ADC31JB68
VDD EN
DAC
DAC38J62
DAC39J84
DAC5670
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of
development. Subject to change or discontinuance without notice.