TPS65177_16 Datasheet, PDF (1/66 Pages) Texas Instruments – Programmable 6-CH LCD Bias IC

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TPS65177, TPS65177A
SLVSBC9C – MARCH 2012 – REVISED FEBRUARY 2016
TPS65177/A Fully I²C Programmable 6-CH LCD Bias IC for all Size TV
Including Gate Pulse Modulation
1 Features
•1 Enable / Disable
– TPS65177: AV_I power cycle
– TPS65177A: V_I power cycle or EN-pin
• 8.6-V to 14.7-V Input Voltage Range
• Non-Synchronous Boost Converter (V_(AVDD))
– Integrated Isolation Switch
– 13.5-V to 19.8-V Output Voltage (I²C)
– 15-V Default Output Voltage
– 4.25-A Switch Current Limit (I²C)
– High Voltage Stress Mode (I²C)
• Synchronous Buck Converter (V_(HAVDD))
– 4.8-V to 11.1-V Output Voltage (I²C)
– 7.5-V Default Output Voltage
– 1.7-A Switch Current Limit
– High Voltage Stress Mode (I²C)
• Non-Synchronous Buck Converter (V_(IO))
– 2.2-V to 3.7-V Output Voltage (I²C)
– 2.5-V Default Output Voltage
– 3-A Switch Current Limit
• Synchronous Buck Converter (V_(CORE))
– 0.8-V to 3.3-V Output Voltage (I²C)
– 1-V Default Output Voltage
– 2.5-A Switch Current Limit
• Positive Charge-Pump Controller (V_(GH))
– 20-V to 40-V Output Voltage (I²C)
– 28-V Default Output Voltage
– Temp. Compensation Offset 0-V to 15-V (I²C)
– 4-V Default Offset (28 V to 32 V)
• Negative Charge-Pump Controller (V_(GL))
– –14.5-V to –5.5-V Output Voltage (I²C)
– –7.9-V Default Output Voltage
• Gate Pulse Modulation (GPM)
– Down to 0-V, 5-V, 10-V or 15-V (I²C)
– 0-V Default Discharge Voltage
• Temperature Compensation for V_(GH)
• Thermal Shutdown
• I²C Compatible Interface
• EEPROM Memory
• 6-mm × 6-mm × 1-mm 40-Pin VQFN Package
2 Applications
• GIP (Gate-in-Panel) LCD TVs
• Non-GIP LCD TVs
3 Description
The TPS65177/A provides all supply rails needed by
a GIP (Gate-in-Panel) or non-GIP TFT-LCD panel. All
output voltages are I²C programmable.
V_(IO) and V_(CORE) for the T-CON, V_(AVDD) and V_(HAVDD)
for the Source Driver and the Gamma Buffer, V_(GH)
and V_(GL) for the Gate Driver or the Level Shifter. For
use with non-GIP technology Gate Pulse Modulation
(GPM) is implemented, for use with GIP technology
the V_(GH) rail can be temperature compensated.
Furthermore a High Voltage Stress Mode (HVS) for
V_(AVDD) and V_(HAVDD) and an integrated V_(AVDD)
Isolation Switch is implemented. V_(CORE), V_(HAVDD),
V_(GH), V_(GL), GPM and the V_(GH) temperature
compensation can be enabled and disabled by I²C
programming.
A single BOM (Bill of Materials) can cover several
panel types and sizes whose desired output voltage
levels can be programmed in production and stored
in a non-volatile integrated memory.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS65177
VQFN (40 Pin)
6.00 mm x 6.00 mm
TPS65177A
VQFN (40 Pin)
6.00 mm x 6.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VI
8.6 V to 14.7 V
I²C
compatible
Block Diagram
Boost Converter
Isolation Switch
Buck Converter 1
Buck Converter 2
(Synchronous)
Buck Converter 3
(Synchronous)
Positive Charge Pump
Controller
(Temp. Compensated)
Negative Charge Pump
Controller
Gate Pulse Modulation
V(A VD D)
13.5 V to 19 V, 2.2 A @ 18 V
V(IO)
2.2 V to 3.7 V, 2.7 A @ 3.3 V
V(C ORE )
0.8 V to 3.3 V, 2.4 A @ 1.2 V
V(H AVDD )
4.8 V to 11.1 V, 1 A @ 9 V
V(GH)
20 V to 40 V, 200 mA
V(GL)
±5.5 V to ±14.5 V, 200 mA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.