TPS53681 Datasheet, PDF (1/125 Pages) Texas Instruments – Dual-Channel (6-Phase + 2-Phase) or (5-Phase + 3-Phase) D-CAP+ Step-Down Multiphase Controller with NVM and PMBus

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TPS53681
SLUSCT1 – JUNE 2017
TPS53681 Dual-Channel (6-Phase + 2-Phase) or (5-Phase + 3-Phase) D-CAP+™ Step-Down
Multiphase Controller with NVM and PMBus™
1 Features
•1 Conversion Input Voltage Range: 4.5 V to 17 V
• 8-Bit DAC with Selectable 5 mV or 10 mV
Resolution and Output Ranges from 0.25 V to
1.52 V or 0.5 to 2.8125 V for Dual Channels
• Phase Configurations
– Maximum (6-Phase + 2-Phase) or (5-Phase +
3-Phase)
– Minimum (1-Phase + 1-Phase)
• Driverless Configuration for Efficient High-
Frequency Switching
• Dynamic Output Voltage Transitions with
Programmable Slew Rates via PMBus Interface
• Frequency Selections with Closed-loop Frequency
Control: 300 kHz to 1 MHz
• Programmable Internal Loop Compensations
• Configurable with Non-Volatile Memory (NVM) for
Low External Component Counts
• Individual Phase Current Calibrations and Reports
• Dynamic Phase Shedding with Programmable
Current Threshold for Optimizing Efficiency at
Light and Heavy Loads
• Fast Phase-Adding for Undershoot Reduction
(USR)
• Fully Compatible with TI NextFET™ Power Stage
for High-Density Solutions
• Accurate, Adjustable Voltage Positioning
• Patented AutoBalance™ Phase Balancing
• Selectable, 16-level Per-Phase Current Limit
• PMBus™ System Interface for Telemetry of
Voltage, Current, Power, Temperature, and Fault
Conditions
• Low Quiescent Current
• 5 mm × 5 mm, 40-Pin, QFN PowerPad™ Package
2 Applications
• ASIC Needs Dual Power Rails
• High-Performance Processor Power
• Networking Processor Power (Broadcom^®,
Cavium^®)
• High-Current FPGA Power (Intel^®, Xilinx^®)
• High-Performance ARM Processor Power
3 Description
The TPS53681 is a multiphase step-down controller
with dual channels, built-in non-volatile memory
(NVM), and PMBus™ interface, and is fully
compatible with TI NexFET ™power stage. Advanced
control features such as D-CAP+™ architecture with
undershoot reduction (USR) provide fast transient
response, low output capacitance, and high
efficiency. The device also provides novel phase
interleaving strategy and dynamic phase shedding for
efficiency improvement at different loads. The device
supports fast dynamic voltage transitions with
adjustable slew rate. In addition, the device supports
the PMBus communication interface for reporting the
telemetry of voltage, current, power, temperature, and
fault conditions to the systems. All programmable
parameters can be configured by the PMBus
interface and can be stored in NVM as the new
default values to minimize the external component
count.
The TPS53681 device is offered in a thermally
enhanced 40-pin QFN packaged and is rated to
operate from –40°C to 125°C.
Device Information⁽¹⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS53681
QFN (40)
5 mm × 5 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Application
TPS53681
PWM1
CSP1
Power
Stage
PMBus
PWM2
CSP2
Power
Stage
PWM6
CSP6
Power
Stage
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.