TPS53659 Datasheet, PDF (1/11 Pages) Texas Instruments – Dual-Channel (4-Phase + 1-Phase) or (3-Phase + 2-Phase) D-CAP+ Step-Down Multiphase Controller with NVM and PMBus for VR13 Server Memory

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TPS53659
SLUSC45 – NOVEMBER 2016
TPS53659 Dual-Channel (4-Phase + 1-Phase) or (3-Phase + 2-Phase) D-CAP+™ Step-Down
Multiphase Controller with NVM and PMBus™ for VR13 Server Memory
1 Device Overview
1.1 Features
1
• Intel VR13 Serial VID (SVID) Compliant
• Full VR13 Server Feature Set Including Digital
Input Power Monitor and PIN_ALT Pin
• Programmable Loop Compensations
• Configurable with Non-Volatile Memory (NVM) for
Low External Component Counts
• Individual Phase Current Calibrations and Reports
• Dynamic Phase Shedding with Programmable
Current Threshold for Optimizing Efficiency at Light
and Heavy Loads
• Fast Phase-Adding for Undershoot Reduction
(USR)
• Backward VR12.0 and VR12.5 Compatible
• 8-Bit DAC with Selectable 5 mV or 10 mV
Resolution and Output Ranges from 0.25 V to
1.52 V or 0.5 to 2.8125 V for Dual Channels
• Driverless Configuration for Efficient High-
Frequency Switching
• Fully Compatible with TI NextFET™ Power Stage
for High-Density Solutions
• Accurate, Adjustable Voltage Positioning
• Frequency Selections with Closed-loop Frequency
Control: 300 kHz to 1 MHz
• Patented AutoBalance™ Phase Balancing
• Selectable, 16-level Per-Phase Current Limit
• PMBus™ System Interface for Telemetry of
Voltage, Current, Power, Temperature, and Fault
Conditions
• Dynamic Output Voltage Transitions with
Programmable Slew Rates via SVID or PMBus
Interface
• Conversion Voltage Range: 4.5 V to 17 V
• Low Quiescent Current
• 5 mm × 5 mm, 40-Pin, QFN PowerPad™ Package
1.2 Applications
• VR13 Memory Power of Server and Telecom
Applications
• ASIC Needs Dual Power Rails
• High-Performance Processor Power
1.3 Description
The TPS53659 is a fully VR13 SVID compliant step-down controller with dual channels, built-in non-
volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET ™power stage.
Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast
transient response, low output capacitance, and good current sharing. The device also provides novel
phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads.
Adjustable control of V_CORE slew rate and voltage positioning round out the Intel^® VR13™ features. In
addition, the device supports the PMBus communication interface for reporting the telemetry of voltage,
current, power, temperature, and fault conditions to the systems. All programmable parameters can be
configured by the PMBus interface and can be stored in NVM as the new default values to minimize the
external component count.
The TPS53659 device if offered in a thermally enhanced 40-pin QFN packaged and is rated to operate
from –40°C to 125°C.
Table 1-1. Device Information⁽¹⁾
PART NUMBER
PACKAGE
TPS53659
QFN (40)
(1) For more information, see, Mechanical, Packaging, and Orderable Information.
BODY SIZE
5 mm × 5 mm
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.