TPIC6C595_15 Datasheet, PDF (1/28 Pages) Texas Instruments – Power Logic 8-Bit Shift Register

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TPIC6C595
SLIS061D – JULY 1998 – REVISED SEPTEMBER 2015
TPIC6C595 Power Logic 8-Bit Shift Register
1 Features
•1 Low r_DS(on), 7 Ω Typical
• Avalanche Energy, 30 mJ
• Eight Power DMOS Transistor Outputs of 100-mA
Continuous Current
• 250-mA Current Limit Capability
• ESD Protection, 2500 V
• Output Clamp Voltage, 33 V
• Devices are Cascadable
• Low-Power Consumption
Outputs are low-side, open-drain DMOS transistors
with output ratings of 33-V to 100-mA continuous
sink-current capability. Each output provides a
250-mA maximum current limit at T_C = 25°C. The
current limit decreases as the junction temperature
increases for additional device protection. The device
also provides up to 2500 V of ESD protection when
tested using the human-body model and the 200-V
machine model.
The TPIC6C595 is characterized for operation over
the operating case temperature range of −40°C to
125°C.
2 Applications
• Instrumentation Clusters
• Tell-Tale Lamps
• LED Illumination and Controls
• Automotive Relay or Solenoids
• Drivers
PART NUMBER
TPIC6C595
Device Information⁽¹⁾
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm × 3.91 mm
TSSOP (16)
5.00 mm × 4.40 mm
PDIP (16)
19.30 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
The TPIC6C595 is a monolithic, medium-voltage,
low-current power 8-bit shift register designed for use
in systems that require relatively moderate load
power such as LEDs. The device contains a built-in
voltage clamp on the outputs for inductive transient
protection. Power driver applications include relays,
solenoids, and other low-current or medium-voltage
loads.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift
register clock (SRCK) and the register clock (RCK),
respectively. The device transfers data out the serial
output (SER OUT) port on the rising edge of SRCK.
The storage register transfers data to the output
buffer when shift register clear (CLR) is high. When
CLR is low, the input shift register is cleared. When
output enable (G) is held high, all data in the output
buffers is held low and all drain outputs are off. When
G is held low, data from the storage register is
transparent to the output buffers. When data in the
output buffers is low, the DMOS transistor outputs are
off. When data is high, the DMOS transistor outputs
have sink-current capability. The SER OUT allows for
cascading of the data from the shift register to
additional devices.
G8
RCK ¹⁰
7
CLR
15
SRCK
2
SER IN
Logic Symbol
EN3
C2
SRG8
R
C1
1D
2
2
3
DRAIN0
4
DRAIN1
5
DRAIN2
6
DRAIN3
11
DRAIN4
12
DRAIN5
13
DRAIN6
14
DRAIN7
9
SER OUT
This symbol is in accordance with
ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.