TPIC6A596_15 Datasheet, PDF (1/16 Pages) Texas Instruments – POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6A596
POWER LOGIC 8ĆBIT SHIFT REGISTER
SLIS094A − MARCH 2000 − REVISED MAY 2005
D Low r_DS(on) . . . 1 Ω Typ
D Output Short-Circuit Protection
NE PACKAGE
(TOP VIEW)
D Avalanche Energy . . . 75 mJ
D Eight 350-mA DMOS Outputs
DRAIN2 ₁
DRAIN3 2
20 ^DRAIN1
19 DRAN0
D 50-V Switching Capability
D Enhanced Cascading for Multiple Stages
D All Registers Cleared With Single Input
D Low Power Consumption
SRCLR 3
G4
PGND 5
PGND 6
RCK 7
18 SER IN
17 V_CC
16 PGND
15 PGND
14 LGND
description
SRCK 8
DRAIN4 9
13 SER OUT
12 DRAIN7
The TPIC6A596 is a monolithic, high-voltage,
DRAIN5 10 11 DRAIN6
high-current power logic 8-bit shift register
designed for use in systems that require relatively
high load power. The device contains a built-in
DW PACKAGE
(TOP VIEW)
voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other medium-
current or high-voltage loads. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit, D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift-
register clock (SRCK) and the register clock
(RCK), respectively. The storage register
DRAIN2 ₁
DRAIN3 ₂
SRCLR ₃
G4
PGND 5
PGND 6
PGND 7
PGND 8
RCK 9
SRCK 10
DRAIN4 11
DRAIN5 12
24 ^DRAIN1
23 ^DRAIN0
22 ^{SER IN}
21 V_CC
20 PGND
19 PGND
18 PGND
17 PGND
16 LGND
15 SER OUT
14 DRAIN7
13 DRAIN6
transfers data to the output buffer when shift-
register clear (SRCLR) is high. When SRCLR is low, all registers in the device are cleared. When output enable
G is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data
from the storage register is transparent to the output buffers. The serial output (SER OUT) is clocked out of the
device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide
improved performance for applications where clock signals may be skewed, devices are not located near one
another, or the system must tolerate electromagnetic interference.
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink
current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high,
the DMOS-transistor outputs have sink current capability.
Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system
flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected
to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND
and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.
The TPIC6A596 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount
(DW) package. The TPIC6A596 is characterized for operation over the operating case temperature range of
−40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2000 − 2005, Texas Instruments Incorporated
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