TPIC6A595DWR Datasheet, PDF (1/17 Pages) Texas Instruments – POWER LOGIC 8-BIT SHIFT REGISTER

TPIC6A595
POWER LOGIC 8ĆBIT SHIFT REGISTER
SLIS005B − APRIL 1993 − REVISED MAY 2005
D Low r_DS(on) . . . 1 Ω Typ
D Output Short-Circuit Protection
NE PACKAGE
(TOP VIEW)
D Avalanche Energy . . . 75 mJ
D Eight 350-mA DMOS Outputs
DRAIN2 ₁
DRAIN3 2
20 ^DRAIN1
19 DRAN0
D 50-V Switching Capability
D Devices Are Cascadable
D Low Power Consumption
SRCLR 3
G4
PGND 5
PGND 6
18 SER IN
17 V_CC
16 PGND
15 PGND
description
RCK 7
SRCK 8
14 LGND
13 SER OUT
The TPIC6A595 is a monolithic, high-voltage,
high-current power logic 8-bit shift register
DRAIN4 9
DRAIN5 ¹⁰
12 DRAIN7
11 _DRAIN6
designed for use in systems that require relatively
high load power. The device contains a built-in
voltage clamp on the outputs for inductive
DW PACKAGE
(TOP VIEW)
transient protection. Power driver applications
include relays, solenoids, and other medium-cur-
rent or high-voltage loads. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.
DRAIN2 ₁
DRAIN3 ₂
SRCLR ₃
G4
PGND 5
24 ^DRAIN1
23 ^DRAIN0
22 ^{SER IN}
21 V_CC
20 PGND
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit, D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shift-
register clock (SRCK) and the register clock
(RCK), respectively. The storage register
transfers data to the output buffer when shift-
PGND 6
PGND 7
PGND 8
RCK 9
SRCK 10
DRAIN4 11
DRAIN5 12
19 PGND
18 PGND
17 PGND
16 LGND
15 SER OUT
14 DRAIN7
13 DRAIN6
register clear (SRCLR) is high. When SRCLR is
low, the input shift register is cleared. When output
enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held
low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) allows for
cascading of the data from the shift register to additional devices.
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink
current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high,
the DMOS-transistor outputs have sink current capability.
Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system
flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected
to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND
and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.
The TPIC6A595 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount
(DW) package. The TPIC6A595 is characterized for operation over the operating case temperature range of
−40°C to 125°C.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1995 − 2005, Texas Instruments Incorporated
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