TPIC6A259_12 Datasheet, PDF (1/13 Pages) Texas Instruments – POWER LOGIC 8-BIT ADDRESSABLE LATCH

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• Low r_DS(on) . . . 1 Ω Typ
• Output Short-Circuit Protection
• Avalanche Energy . . . 75 mJ
• Eight 350-mA DMOS Outputs
• 50-V Switching Capability
• Four Distinct Function Modes
• Low Power Consumption
description
This power logic 8-bit addressable latch controls
open-drain DMOS-transistor outputs and is
designed for general-purpose storage appli-
cations in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multi-
functional device capable of operating as eight
addressable latches or an 8-line demultiplexer
with active-low DMOS outputs. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.
Four distinct modes of operation are selectable by
controlling the clear (CLR) and enable (G) inputs
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS-transistor output inverts the
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G should be held high (inactive) while the
address lines are changing. In the 8-line
demultiplexing mode, the addressed output is
inverted with respect to the D input and all other
outputs are high. In the clear mode, all outputs are
high and unaffected by the address and data
inputs.
Separate power ground (PGND) and logic ground
(LGND) terminals are provided to facilitate
maximum system flexibility. All PGND terminals
are internally connected, and each PGND
terminal must be externally connected to the
power system ground in order to minimize
parasitic impedance. A single-point connection
between LGND and PGND must be made
externally in a manner that reduces crosstalk
between the logic and load circuits.
TPIC6A259
POWER LOGIC 8ĆBIT ADDRESSABLE LATCH
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SLIS004B − APRIL 1993 − REVISED SEPTEMBER 1995
NE PACKAGE
(TOP VIEW)
DRAIN2 ₁
DRAIN3 2
S1 3
LGND 4
PGND 5
PGND 6
S2 7
G8
DRAIN4 9
DRAIN5 10
20 ^DRAIN1
19 DRAIN0
18 S0
17 V_CC
16 PGND
15 PGND
14 CLR
13 D
12 DRAIN7
11 DRAIN6
DW PACKAGE
(TOP VIEW)
DRAIN2 ₁
DRAIN3 ₂
S1 ₃
LGND 4
PGND 5
PGND 6
PGND 7
PGND 8
S2 9
G 10
DRAIN4 11
DRAIN5 12
24 ^DRAIN1
23 ^DRAIN0
22 ^S0
21 V_CC
20 PGND
19 PGND
18 PGND
17 PGND
16 CLR
15 D
14 DRAIN7
13 DRAIN6
INPUTS
CLR G D
H LH
H LL
H HX
L LH
L LL
L HX
FUNCTION TABLE
OUTPUT OF
ADDRESSED
DRAIN
L
H
Qio
L
H
H
EACH
OTHER
DRAIN
Qio
Qio
Qio
H
H
H
FUNCTION
Addressable
Latch
Memory
8-Line
Demultiplexer
Clear
LATCH SELECTION TABLE
SELECT INPUTS
S2 S1 S0
LL L
LLH
LH L
LHH
HL L
HL H
HH L
HH H
DRAIN
ADDRESSED
0
1
2
3
4
5
6
7
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1995, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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