TPIC5424L Datasheet, PDF (1/15 Pages) Texas Instruments – H-BRIDGE LOGIC-LEVEL POWER DMOS ARRAY

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TPIC5424L
HĆBRIDGE LOGICĆLEVEL POWER DMOS ARRAY
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SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994
• Low r_DS(on) . . . 0.4 Ω Typ
• High-Voltage Output . . . 60 V
• Pulsed Current . . . 3 A Per Channel
• Fast Commutation Speed
• Direct Logic-Level Interface
description
The TPIC5424L is a monolithic logic-level power
DMOS array that consists of four electrically
isolated N-channel enhancement-mode DMOS
transistors, two of which are configured with a
common source.
DW PACKAGE
(TOP VIEW)
GND ₁
SOURCE4/GND 2
GATE4 3
NC 4
DRAIN4 5
SOURCE3 6
DRAIN3 7
GATE3 8
NC 9
NC 10
20 ^SOURCE2/GND
19 GATE2
18 NC
17 NC
16 DRAIN2
15 SOURCE1
14 DRAIN1
13 GATE1
12 NC
11 NC
The TPIC5424L is offered in a 16-pin thermally
enhanced dual-in-line (NE) package and a 20-pin
wide-body surface-mount (DW) package. The
TPIC5424L is characterized for operation over the
case temperature range of − 40°C to 125°C.
NC − No internal connection
NE PACKAGE
(TOP VIEW)
DRAIN2 1
SOURCE2/GND 2
GATE2 3
GND 4
GND 5
GATE4 6
SOURCE4/GND 7
DRAIN4 8
16 SOURCE1
15 DRAIN1
14 GATE1
13 GND
12 GND
11 GATE3
10 DRAIN3
9 SOURCE3
schematic
DRAIN1
Q1
GATE1
Z1
D1 D2
DRAIN3
Q3
Z3
GATE3
SOURCE1
DRAIN2
Q2
GATE2
Z2
SOURCE3
DRAIN4
Q4
Z4
GATE4
GND, SOURCE2, SOURCE4
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1994, Texas Instruments Incorporated
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