TPIC5421L Datasheet, PDF (1/16 Pages) Texas Instruments – H-BRIDGE GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY

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• Low r_DS(on) . . . 0.4 Ω Typ
• Voltage Output . . . 60 V
• Input Protection Circuitry . . . 18 V
• Pulsed Current . . . 3 A Per Channel
• Extended ESD Capability . . . 4000 V
• Direct Logic-Level Interface
description
The TPIC5421L is a monolithic gate-protected
logic-level power DMOS array that consists of four
electrically isolated N-channel enhancement-
mode DMOS transistors, two of which are
configured with common source. Each transistor
features integrated high-current zener diodes
(Z_CXa and Z_CXb) to prevent gate damage in the
event that an overstress condition occurs. These
zener diodes also provide up to 4000 V of ESD
protection when tested using the human-body
model of a 100-pF capacitor in series with a 1.5-kΩ
resistor.
The TPIC5421L is offered in a 20-pin wide-body
surface-mount (DW) package and a 16-pin
thermally-enhanced dual-in-line (NE) package
and is characterized for operation over the case
temperature of −40°C to 125°C.
TPIC5421L
HĆBRIDGE GATEĆPROTECTED LOGICĆLEVEL
POWER DMOS ARRAY
SLIS027A − OCTOBER 1994 − REVISED OCTOBER 1995
DW PACKAGE
(TOP VIEW)
GND ₁
SOURCE4/GND 2
GATE4 3
NC 4
DRAIN4 5
SOURCE3 6
DRAIN3 7
GATE3 8
NC 9
NC 10
20 ^SOURCE2/GND
19 GATE2
18 NC
17 NC
16 DRAIN2
15 SOURCE1
14 DRAIN1
13 GATE1
12 NC
11 NC
NE PACKAGE
(TOP VIEW)
DRAIN2 1
SOURCE2/GND 2
GATE2 3
GND 4
GND 5
GATE4 6
SOURCE4/GND 7
DRAIN4 8
16 SOURCE1
15 DRAIN1
14 GATE1
13 GND
12 GND
11 GATE3
10 DRAIN3
9 SOURCE3
NC − No internal connection
schematic
14
DRAIN1
Q1
GATE1 ¹³
ZC1b
Z1
D1 D2
Z3
ZC1a
SOURCE1 ¹⁵
DRAIN2 ¹⁶
Q2
19
GATE2
Z2
Z4
ZC2b
ZC2a
1, 2, 20
GND, SOURCE2, SOURCE4
NOTE A: For correct operation, no terminal may be taken below GND.
Pin numbers shown are for the DW package.
7
DRAIN3
Q3
8 _GATE3
ZC3b
ZC3a
6 _SOURCE3
5 _DRAIN4
Q4
3 _GATE4
ZC4b
ZC4a
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1995, Texas Instruments Incorporated
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