TPIC5323L Datasheet, PDF (1/13 Pages) Texas Instruments – 3-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY

TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL
POWER DMOS ARRAY
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
D Low r_DS(on) . . . 0.6 Ω Typ
D Voltage Output . . . 60 V
D PACKAGE
(TOP VIEW)
D Input Protection Circuitry . . . 18 V
D Pulsed Current . . . 3 A Per Channel
D Extended ESD Capability . . . 4000 V
D Direct Logic-Level Interface
DRAIN2 1
DRAIN2 2
SOURCE2 3
SOURCE2 4
16 GATE1
15 SOURCE1
14 SOURCE1
13 DRAIN1
GATE2 5 12 DRAIN1
description
DRAIN3 6 11 SOURCE3
The TPIC5323L is a monolithic gate-protected
logic-level power DMOS array that consists of
DRAIN3 7
GND 8
10 SOURCE3
9 GATE3
three electrically isolated independent N-channel
enhancement-mode DMOS transistors. Each transistor features integrated high-current zener diodes (Z_CXa
and Z_CXb) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also
provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series
with a 1.5-kΩ resistor.
The TPIC5323L is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized
for operation over the case temperature of – 40°C to 125°C.
schematic
DRAIN1
12, 13
GATE2
5
DRAIN2
1, 2
GATE3
9
DRAIN3
6, 7
Q1
GATE1 ¹⁶
ZC1b
ZC1a
D1
Q2
Z1
ZC2b
ZC2a
D2
Q3
Z2
ZC3b
ZC3a
D3
Z3
14, 15
8
SOURCE1 GND
3, 4
SOURCE2
NOTE A: For correct operation, no terminal can be taken below GND.
10, 11
SOURCE3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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Copyright © 1995, Texas Instruments Incorporated
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