TPIC5303 Datasheet, PDF (1/14 Pages) Texas Instruments – 3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY

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TPIC5303
3ĆCHANNEL INDEPENDENT GATEĆPROTECTED
POWER DMOS ARRAY
SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995
• Low r_DS(on) . . . 0.4 Ω Typ
• High Voltage Output . . . 60 V
D PACKAGE
(TOP VIEW)
• Extended ESD Capability . . . 4000 V
• Pulsed Current . . . 5 A Per Channel
• Fast Commutation Speed
DRAIN2 1
DRAIN2 2
SOURCE2 3
16 GATE1
15 SOURCE1
14 SOURCE1
description
SOURCE2 4
GATE2 5
13 DRAIN1
12 DRAIN1
The TPIC5303 is a monolithic gate-protected
power DMOS array that consists of three
independent electrically isolated N-channel
DRAIN3 6
DRAIN3 7
GND 8
11 SOURCE3
10 SOURCE3
9 GATE3
enhancement-mode DMOS transistors. Each
transistor features integrated high-current zener
diodes (Z_CXa and Z_CXb) to prevent gate damage in the event that an overstress condition occurs. These zener
diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF
capacitor in series with a 1.5-kΩ resistor.
The TPIC5303 is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized for
operation over the case temperature range of − 40°C to 125°C.
schematic
DRAIN1
12, 13
GATE2
5
DRAIN2
1, 2
GATE3
9
DRAIN3
6, 7
Q1
GATE1 ¹⁶
ZC1b
ZC1a
D1
Q2
Z1
ZC2b
ZC2a
D2
Q3
Z2
ZC3b
ZC3a
D3
Z3
14, 15
8
SOURCE1 GND
3, 4
SOURCE2
NOTE A: For correct operation, no terminal pin may be taken below GND.
10, 11
SOURCE3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1995, Texas Instruments Incorporated
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