TPIC5203 Datasheet, PDF (1/13 Pages) Texas Instruments – 2-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY

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TPIC5203
2ĆCHANNEL INDEPENDENT GATEĆPROTECTED
POWER DMOS ARRAY
SLIS040 − SEPTEMBER 1994
• Low r_DS(on) . . . 0.26 Ω Typ
• High Voltage Output . . . 60 V
D PACKAGE
(TOP VIEW)
• Extended ESD Capability . . . 4000 V
• Pulsed Current . . . 8 A Per Channel
• Fast Commutation Speed
GND 1
SOURCE1 2
GATE2 3
8 DRAIN1
7 GATE1
6 SOURCE2
DRAIN2 4
5 NC
description
NC − No internal connection
The TPIC5203 is a monolithic gate-protected
power DMOS array that consists of two
independent electrically isolated N-channel enhancement-mode DMOS transistors. Each transistor features
integrated high-current zener diodes (Z_CXa and Z_CXb) to prevent gate damage in the event that an overstress
condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the
human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor.
The TPIC5203 is offered in a standard eight-pin small-outline surface-mount (D) package and is characterized
for operation over the case temperature range of − 40°C to 125°C.
schematic
DRAIN1
8
GATE2
3
DRAIN2
4
Q1
7
GATE1
ZC1b
ZC1a
D1
Z1
Q2
D2
Z2
ZC2b
ZC2a
2
SOURCE1
1
GND
6
SOURCE2
NOTE: For correct operation, no terminal pin may be taken below GND.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1994, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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