TPIC1301 Datasheet, PDF (1/14 Pages) Texas Instruments – 3-HALF H-BRIDGE GATE-PROTECTED POWER DMOS ARRAY

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TPIC1301
3ĆHALF HĆBRIDGE GATEĆPROTECTED
POWER DMOS ARRAY
SLIS037 − NOVEMBER 1994
• Low r_DS(on) . . . 0.23 Ω Typ
• High Voltage Output . . . 60 V
DW PACKAGE
(TOP VIEW)
• Extended ESD Capability . . . 4000 V
OUTPUT1 ₁
24 ^OUTPUT1
• Pulsed Current . . . 11.25 A Per Channel
• Fast Commutation Speed
GATE4 ₂
SOURCE4 ₃
SOURCE4 4
23 ^GATE1
22 ^DRAIN1
21 DRAIN1
description
GND 5
GND 6
20 DRAIN2
19 DRAIN2
The TPIC1301 is a monolithic gate-protected
GATE5 7
18 OUTPUT2
power DMOS array that consists of six electrically
SOURCE6 8
17 OUTPUT2
isolated N-channel enhancement-mode DMOS
SOURCE6 9
16 GATE2
transistors configured as three half H-bridges.
GATE6 10 15 DRAIN3
Each transistor features integrated high-current
zener diodes (Z_{CXa and} Z_CXb) to prevent gate
damage in the event that an overstress condition
OUTPUT3 11
OUTPUT3 12
14 DRAIN3
13 GATE3
occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the human-body
model of a 100-pF capacitor in series with a 1.5-kΩ resistor.
The TPIC1301 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of − 40°C to 125°C.
schematic
21, 22
DRAIN1
Q1
23
GATE1
ZC1b
ZC1a
1, 24
OUTPUT1
OUTPUT2
17, 18
GATE5
7
GATE2 DRAIN2
16
19, 20
Z1
D1
D4
Q2
ZC2b
ZC2a
Z2
Z3
D2 D3
D5
14, 15
DRAIN3
Q3
13
GATE3
ZC3b
ZC3a
11, 12 _OUTPUT3
Q4
Q5
2
Z4
GATE4
Z5
ZC4b
ZC5b
ZC4a
SOURCE4 ^{3, 4}
ZC5a
5, 6
GND
NOTE: For correct operation, no terminal pin may be taken below GND.
Q6
Z6
10
GATE6
ZC6b
ZC6a
8, 9 _SOURCE6
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1994, Texas Instruments Incorporated
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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