TP3054-X_15 Datasheet, PDF (1/22 Pages) Texas Instruments – Extended Temperature Serial Interface CODEC/Filter COMBO Family

TP3054-X, TP3057-X
www.ti.com
SNOSBY2C – MARCH 2005 – REVISED APRIL 2013
Extended Temperature Serial Interface CODEC/Filter COMBO Family
Check for Samples: TP3054-X, TP3057-X
FEATURES
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•2 −40°C to +85°C Operation
• Complete CODEC and Filtering System
(COMBO) Including:
– Transmit High-Pass and Low-Pass Filtering
– Receive Low-Pass Filter with Sin x/x
Correction
– Active RC Noise Filters
– μ-Law or A-Law Compatible COder and
DECoder
– Internal Precision Voltage Reference
– Serial I/O Interface
– Internal Auto-Zero Circuitry
• μ-Law, 16-Pin - TP3054
• A-Law, 16-Pin - TP3057
• Designed for D3/D4 and CCITT Spplications
• ±5V Operation
• Low Operating Power - Typically 50 mW
• Power-Down Standby Mode - Typically 3 mW
• Automatic Power-Down
• TTL or CMOS Compatible Digital Interfaces
• Maximizes Line Interface Card Circuit Density
• Dual-In-Line or PCC Surface Mount Packages
• See also AN-370, “Techniques for Designing
with CODEC/Filter COMBO Circuits”
(SNLA136)
DESCRIPTION
The TP3054, TP3057 family consists of μ-law and A-
law monolithic PCM CODEC/filters utilizing the A/D
and D/A conversion architecture shown in Figure 3,
and a serial PCM interface. The devices are
fabricated using TI's advanced double-poly CMOS
process (microCMOS).
The encode portion of each device consists of an
input gain adjust amplifier, an active RC pre-filter
which eliminates very high frequency noise prior to
entering a switched-capacitor band-pass filter that
rejects signals below 200 Hz and above 3400 Hz.
Also included are auto-zero circuitry and a
companding coder which samples the filtered signal
and encodes it in the companded μ-law or A-law
PCM format. The decode portion of each device
consists of an expanding decoder, which reconstructs
the analog signal from the companded μ-law or A-law
code, a low-pass filter which corrects for the sin x/x
response of the decoder output and rejects signals
above 3400 Hz followed by a single-ended power
amplifier capable of driving low impedance loads. The
devices require two 1.536 MHz, 1.544 MHz or
2.048 MHz transmit and receive master clocks, which
may be asynchronous; transmit and receive bit
clocks, which may vary from 64 kHz to 2.048 MHz;
and transmit and receive frame sync pulses. The
timing of the frame sync pulses and PCM data is
compatible with both industry standard formats.
Connection Diagram
Figure 1. Plastic Chip Carriers (Top View)
Package Number FN0020A
Figure 2. Dual-In-Line Package (Top View)
Package Number NFG001E & DW0016B
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2
PRODUCTION DATA information is current as of publication date.
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Instruments standard warranty. Production processing does not
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