TMS320F28377D_14 Datasheet, PDF (1/121 Pages) Texas Instruments – Dual-Core Delfino™ Microcontrollers

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TMS320F28377D, TMS320F28376D, TMS320F28375D, TMS320F28374D
SPRS880A – DECEMBER 2013 – REVISED MARCH 2014
TMS320F2837xD Dual-Core Delfino™ Microcontrollers
1 Device Overview
1.1 Features
1
• Dual-Core Architecture
– Two TMS320C28x 32-Bit CPUs
– 200 MHz (5-ns Cycle Time)
– IEEE 754 Single-Precision Floating-Point Unit
(FPU)
– Trigonometric Math Unit (TMU)
– Viterbi/Complex Math Unit (VCU-II)
– 16 x 16 and 32 x 32 MAC Operations
– 16 x 16 Dual MAC
– Three 32-Bit CPU Timers per Core
– Harvard Bus Architecture
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
• Two Programmable Control Law Accelerators
(CLAs)
– 200 MHz (5-ns Cycle Time)
– 32-Bit Floating-Point Math Accelerator
(IEEE 754 Single Precision)
– Executes Code Independently of Main CPU
• On-Chip Memory
– Up to 1MB Flash, Up to 204KB RAM
– Boot ROM (64KB)
• Serial Peripheral Interface (SPI), Inter-
Integrated Circuit (I²C), Controller Area
Network (CAN), and Parallel I/O Software
Boot Modes
• Standard Math Tables
• System Peripherals
– Dual 32- and 16-Bit EMIF With ASRAM and
SDRAM Support
– Dual 6-Channel DMA Controller
– Up to 169 Individually Programmable,
Multiplexed General-Purpose Input/Output
(GPIO) Pins With Input Filtering
• Communications Peripherals
– USB 2.0 + PHY Port
– Support for 12-Pin 3.3 V-Compatible Universal
Parallel Port (uPP) Interface
– Two CAN-Bus Ports (32 Mailboxes Each)
– Three High-Speed (40-MHz) SPI Ports With 16-
Level FIFO, DMA Support, and
CLA-Accessible
– Two Multichannel Buffered Serial Ports
(McBSPs)
– Four Serial Communications Interfaces (SCIs)
– Two I²C Interfaces
1
• Analog Subsystem
– Four Dual-Mode Analog-to-Digital Converters
(ADCs)
– 16-Bit Mode
• 1.1 MSPS Each (Up to 4.4-MSPS System)
• Differential
• External Reference
• Up to 12 External Channels
– 12-Bit Mode
• 3.5 MSPS Each (Up to 14-MSPS System)
• Single-Ended or Differential
• External Reference
• Up to 24 External Channels
– Single Sample-and-Hold (S/H)
(Four-Simultaneous-S/H System)
– Integrated Post-Processing of ADC Conversions
• Saturating Offset Calibration
• Error From Setpoint Calculation
• High, Low, and Zero-Crossing Compare,
With Interrupt Capability
• Trigger-to-Sample Delay Capture
– Analog Comparator/Digital-to-Analog Converter
(DAC) Subsystem With Glitch Filter, for
Windowed Trip Monitor and PCMC Interfaces
• Eight Windowed Comparators With 12-Bit
DAC References
– Three 12-Bit Buffered DAC Outputs
• Enhanced Control Peripherals
– 24 PWM Channels With Enhanced Features
– 16 High-Resolution PWM Channels
• High-Resolution on Both A and B Channels
of 8 PWM Modules
• Dead-Band Support (on Both Standard and
High-Resolution)
– Six Enhanced Capture (eCAP) Modules
– Three Enhanced Quadrature Encoder Pulse
(eQEP) Modules
– Two Sigma-Delta Filter Modules With up to
8 Input Channels, and PWM Synchronization
• Expanded Peripheral Interrupt (ePIE) Block
– Supports up to 192 Peripheral Interrupts
– GPIO Pins can be Connected to 5 Core
Interrupts
• JTAG Boundary Scan Support ⁽¹⁾
(1) IEEE Standard 1149.1-1990 Standard Test Access Port and
Boundary Scan Architecture
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.