TMS320DM355_15 Datasheet, PDF (1/163 Pages) Texas Instruments – Digital Media System-on-Chip (DMSoC)

TMS320DM355
www.ti.com
SPRS463G – SEPTEMBER 2007 – REVISED JUNE 2010
TMS320DM355
Digital Media System-on-Chip (DMSoC)
Check for Samples: TMS320DM355
1 TMS320DM355 Digital Media System-on-Chip (DMSoC)
1.1 Features
123
• Highlights
– High-Performance Digital Media
System-on-Chip (DMSoC)
– Up to 270-MHz ARM926EJ-S™ Clock Rate
– MPEG4/JPEG Coprocessor Supports
• Up to 720p MPEG4 SP
• Up to 50M Pixels per Second JPEG
– Video Processing Subsystem
• Hardware IPIPE for Real-Time Image
Processing
• Up to 14-bit CCD/CMOS Digital Interface
• Histogram Module
• Resize Image 1/16x to 8x
• Hardware On-Screen Display
• Supports digital HDTV (720p/1080i) output
for connection to external encoder
– Peripherals include DDR and mDDR SDRAM,
2 MMC/SD/SDIO and SmartMedia Flash Card
Interfaces, USB 2.0, 3 UARTs and 3 SPIs
– Configurable Power-Saving Modes
– On-Chip ARM ROM Bootloader (RBL) to Boot
From NAND Flash, MMC/SD, or UART
– Extended Temperature 135- and 216-MHz
Devices are Available
– 3.3-V and 1.8-V I/O, 1.3-V Core
– Debug Interface Support
– 337-Pin Ball Grid Array at 65 nm Process
Technology
• High-Performance Digital Media
System-on-Chip (DMSoC)
– 135-, 216-, and 270-MHz ARM926EJ-S™
Clock Rate
– Fully Software-Compatible With ARM9™
– Extended temperature support for 135- and
216-MHz devices
• ARM926EJ-S Core
– Support for 32-Bit and 16-Bit (Thumb Mode)
Instruction Sets
– DSP Instruction Extensions and Single Cycle
MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ Logic for Real-Time
Debug
• ARM9 Memory Architecture
– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 32K-Byte RAM
– 8K-Byte ROM
– Little Endian
• MPEG4/JPEG Coprocessor
– Fixed Function Coprocessor Supports:
• MPEG4 SP Codec at HD (720p), D1, VGA,
SIF
• JPEG Codec up to 50M Pixels per Second
• Video Processing Subsystem
– Front End Provides:
• Hardware IPIPE for Real-Time Image
Processing
• Up to 14-bit CCD/CMOS Digital Interface
• 16-/8-bit Generic YcBcR-4:2 Interface
(BT.601)
• 10-/8-bit CCIR6565/BT655 Interface
• Up to 75-MHz Pixel Clock
• Histogram Module
• Resize Engine
– Resize Images From 1/16x to 8x
– Separate Horizontal/Vertical Control
– Two Simultaneous Output Paths
– Back End Provides:
• Hardware On-Screen Display (OSD)
• Composite NTSC/PAL video encoder
output
• 8-/16-bit YCC and Up to 18-Bit RGB666
Digital Output
• BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
• Supports digital HDTV (720p/1080i) output
for connection to external encoder
• External Memory Interfaces (EMIFs)
– DDR2 and mDDR SDRAM 16-bit wide EMIF
1
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PRODUCTION DATA information is current as of publication date.
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Instruments standard warranty. Production processing does not
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