TM4EJ64KPU Datasheet, PDF (1/24 Pages) Texas Instruments – EXTENDED-DATA-OUT DYNAMIC RAM MODULES ── SODIMM

TM4EJ64KPU, TM4EJ64NPU, TM4FJ64KPU, TM4FJ64NPU, 4ā194ā304 BY 64ĆBIT
TM8EJ64KPU, TM8EJ64NPU, TM8FJ64KPU, TM8FJ64NPU, 8ā388ā608 BY 64ĆBIT
EXTENDEDĆDATAĆOUT DYNAMIC RAM MODULES Ċ SODIMM
SMMS693A − AUGUST 1997 − REVISED NOVEMBER 1997
D Organization
− TM4xJ64xPU-xx . . . 4 194 304 × 64 Bits
− TM8xJ64xPU-xx . . . 8 388 608 × 64 Bits
D Single 3.3-V Power Supply
(±10% Tolerance)
D JEDEC 144-Pin Small-Outline Dual-In-Line
Memory Module (SODIMM) Without Buffer
for Use With Socket
D TM4xJ64xPU-xx — Utilizes Four 64M-Bit
High-Speed (4M × 16-Bit) Dynamic RAMs
D TM4xJ64xPU-xx — Utilizes Eight 64M-Bit
High-Speed (4M × 16-Bit) Dynamic RAMs
D High-Speed, Low-Noise LVTTL Interface
D High-Reliability 50-Lead 400-Mil-Wide
Surface-Mount Thin Small-Outline Package
(TSOP) (DGE Suffix)
D 3-State Output
D Gold-Plated Contacts
D Long Refresh Periods:
− TMxEJ64KPU: 64 ms (4 096 Cycles)
− TMxEJ64NPU: 64 ms (8 192 Cycles)
− TMxFJ64KPU: 128 ms (4 096 Cycles)
− TMxFJ64NPU: 128 ms (8 192 Cycles)
D Extended Data Out (EDO) Operation With
CAS-Before-RAS (CBR), RAS-Only, and
Hidden Refresh
D Serial Presence-Detect (SPD) Using
EEPROM
D Ambient Temperature Range
0°C to 70°C
D Performance Ranges
ACCESS ACCESS ACCESS EDO
TIME
TIME TIME CYCLE
tRAC
(MAX)
tCAC
tAA tHPC
(MAX) (MAX) (MIN)
’xxJ64xPU-40 40 ns
11 ns 20 ns 16 ns
’xxJ64xPU-50 50 ns
13 ns 25 ns 20 ns
’xxJ64xPU-60 60 ns
15 ns 30 ns 25 ns
description
The TM4xJ64KPU is a 32M-byte, 144-pin, small-outline dual-in-line memory module (SODIMM). The SODIMM
is composed of four TMS465169/P, 4 194 304 × 16-bit 4K normal or low-power battery-backup refresh EDO
dynamic random-access memory (DRAM) devices, each in a 400-mil, 50-pin plastic thin small-outline package
(TSOP) (DGE suffix) package mounted on a substrate with decoupling capacitors. See the TMS465169/P data
sheet (literature number SMHS566).
The TM4xJ64NPU is a 32M-byte, 144-pin SODIMM. The SODIMM is composed of four TMS464169/P,
4 194 304 × 16-bit 8K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors. See the TMS464169/P data sheet
(literature number SMHS566).
The TM8xJ64KPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS465169/P,
4 194 304 × 16-bit 4K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors.
The TM8xJ64NPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS464169/P,
4 194 304 × 16-bit 8K normal or low-power battery-backup refresh EDO DRAMs, each in a 400-mil, 50-pin plastic
TSOP (DGE suffix) mounted on a substrate with decoupling capacitors.
operation
The TM4xJ64xPU operates as four TMS46x169/Ps that are connected as shown in the TMxxJ64xPU functional
block diagram. The TM8xJ64xPU operates as eight TMS46x169/Ps that are connected as shown in the
TMxxJ64xPU functional block diagram.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Copyright  1997, Texas Instruments Incorporated
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