TM497MBK36Q Datasheet, PDF (1/9 Pages) Texas Instruments – 4194304 BY 36-BIT DYNAMIC RAM MODULE

D Organization . . . 4 194 304 × 36
D Single 5-V Power Supply (±10% Tolerance)
D 72-Pin Single-In-Line Memory Module
(SIMM) for Use With Sockets
D Utilizes Eight 16-Megabit DRAMs in Plastic
Small-Outline J-Lead (SOJ) Packages and
Four 4-Megabit DRAMs in Plastic
Small-Outline J-Lead (SOJ) Packages
D Long Refresh Period
32 ms (2048 Cycles)^†
D All Inputs, Outputs, Clocks Fully TTL
Compatible
D Common CAS Control for Nine Common
Data-In and Data-Out Lines in Four Blocks
D Separate RAS Control for Eighteen Data-In
and Data-Out Lines in Two Blocks
D 3-State Output
TM497MBK36A, TM497MBK36Q
4194304 BY 36-BIT
DYNAMIC RAM MODULE
SMMS446C – DECEMBER 1992 – REVISED JUNE 1995
D Performance Ranges:
ACCESS
TIME
tRAC
(MAX)
ACCESS ACCESS READ
TIME TIME OR
tCAC
tAA WRITE
CYCLE
(MAX) (MAX) (MIN)
’497MBK36A-60 60 ns
15 ns 30 ns 110 ns
’497MBK36A-70 70 ns
18 ns 35 ns 130 ns
’497MBK36A-80 80 ns
20 ns 40 ns 150 ns
D Low Power Dissipation
D Operating Free-Air Temperature Range
0°C to 70°C
D Presence Detect
D Gold-Tabbed Version Available:^‡
TM497MBK36A
D Tin-Lead (Solder) Tabbed Version
Available: TM497MBK36Q
description
The TM497MBK36A is a 16M-byte dynamic random-access memory (DRAM) organized as four times
4 194 304 × 9 (bit 9 is generally used for parity) in a 72-pin leadless single-in-line memory module (SIMM). The
SIMM is composed of eight TMS417400DJ, 4 194 304 × 4-bit DRAMs, each in 24/26-lead plastic SOJ packages,
and four TMS44100DJ, 4 194 304 × 1-bit DRAMs, each in 20 / 26-lead plastic SOJ packages mounted on a
substrate with decoupling capacitors. Each TMS417400DJ and TMS44100DJ is described in the TMS417400
and TMS44100 data sheets (respectively).
The TM497MBK36A is available in a double-sided BK leadless module for use with sockets. The
TM497MBK36A features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for operation
from 0°C to 70°C.
operation
The TM497MBK36A operates as eight TMS417400DJs and four TMS44100DJs connected as shown in the
functional block diagram and Table 1. Refer to the TMS417400 and TMS44100 data sheets for details of
operation. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
refresh
The refresh period is extended to 32 ms and, during this period, each of the 2048 rows must be strobed with
RAS in order to retain data. Address line A10 must be used as most significant refresh address line (lowest
frequency) to assure correct refresh for both TMS417400 and TMS44100. A0 – A9 address lines must be
refreshed every 16 ms as required by the TMS44100 DRAM. CAS can remain high during the refresh sequence
to conserve power.
power up
To achieve proper operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is
required after full V_CC level is achieved. These eight initialization cycles need to include at least one refresh
[RAS-only or CAS-before-RAS ( CBR)] cycle.
† _{A0 – A9 address lines must be refreshed every 16 ms.}
‡ _{Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.}
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1995, Texas Instruments Incorporated
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
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