TM497MBK36H Datasheet, PDF (1/9 Pages) Texas Instruments – 4194304 BY 36-BIT DYNAMIC RAM MODULES

D Organization . . . 4 194 304 × 36
D Single 5-V Power Supply (±10% Tolerance)
D 72-Pin Single-In-Line Memory Module
(SIMM) for Use With Sockets
D Uses Eight 16M-bit Dynamic RAMs
(DRAMs) in Plastic Small-Outline J-Lead
(SOJ) Packages and Four 4M-bit DRAMs in
Plastic SOJ Packages
D Long Refresh Period . . . 32 ms
(2 048 Cycles)^†
D All Inputs, Outputs, and Clocks are Fully
TTL Compatible
D Common CAS Control for Nine Common
Data-In and Data-Out Lines in Four Blocks
D Separate RAS Control for Eighteen Data-In
and Data-Out Lines in Two Blocks
TM497MBK36H, TM497MBK36I
4194304 BY 36-BIT
DYNAMIC RAM MODULES
SMMS676 – MARCH 1997
D 3-State Output
D Performance Ranges:
ACCESS
TIME
tRAC
(MAX)
ACCESS ACCESS READ
TIME TIME OR
tCAC
tAA WRITE
CYCLE
(MAX) (MAX) (MIN)
’497MBK36H / I-60 60 ns
’497MBK36H / I-70 70 ns
’497MBK36H / I-80 80 ns
15 ns
18 ns
20 ns
D Low Power Dissipation
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
D Operating Free-Air Temperature
Range . . . 0°C to 70°C
D Presence Detect
D Gold-Tabbed Version Available
TM497MBK36H
D Tin-Lead (Solder) Tabbed Version
Available: TM497MBK36I
description
The TM497MBK36H / I is a 144M-bit dynamic random-access memory (DRAM) device organized as four times
4 194 304 × 9 (bit 9 generally is used for parity) in a 72-pin leadless single-in-line memory module (SIMM). The
SIMM is composed of eight TMS417400ADJ, 4 194 304 × 4-bit DRAMs in 24/26-lead plastic SOJ packages,
and four TMS44100DJ, 4 194 304 × 1-bit DRAMs in 20/26-lead plastic SOJ packages mounted on a substrate
with decoupling capacitors. TMS417400ADJ and TMS44100DJ are described in the TMS417400A and
TMS44100 data sheets (literature numbers SMKS889 and SMHS561, respectively).
The TM497MBK36H / I is available in a double-sided, BK, leadless module for use with sockets. The
TM497MBK36H/ I features RAS access times of 60, 70, and 80 ns. This device is characterized for operation
from 0°C to 70°C.
operation
The TM497MBK36H / I operates as eight TMS417400ADJs and four TMS44100DJs connected as shown in the
functional block diagram and Table 1. See the TMS417400A and TMS44100 data sheets for details of operation.
The common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
Table 1. Connection Table
DATA BLOCK
DQ0 – DQ8
DQ9 – DQ17
DQ18 – DQ26
DQ27 – DQ35
RASx
RAS0
RAS0
RAS2
RAS2
CASx
CAS0
CAS1
CAS2
CAS3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
† _{A0 – A9 address lines must be refreshed every 16 ms.}
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  1997, Texas Instruments Incorporated
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