English
Language : 

TLV320AIC3254_14 Datasheet, PDF (1/53 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TLV320AIC3254
SLAS549D – SEPTEMBER 2008 – REVISED NOVEMBER 2014
TLV320AIC3254 Ultra Low Power Stereo Audio Codec with Embedded miniDSP
1 Features
•1 Stereo Audio DAC with 100dB SNR
• 4.1mW Stereo 48ksps DAC Playback
• Stereo Audio ADC with 93dB SNR
• 6.1-mW Stereo 48-ksps ADC Record
• PowerTune™
• Extensive Signal Processing Options
• Embedded miniDSP
• Six Single-Ended or Three Fully-Differential
Analog Inputs
• Stereo Analog and Digital Microphone Inputs
• Stereo Headphone Outputs
• Stereo Line Outputs
• Very Low-Noise PGA
• Low Power Analog Bypass Mode
• Programmable Microphone Bias
• Programmable PLL
• Integrated LDO
• 5 mm x 5 mm 32-pin QFN Package
2 Applications
• Portable Navigation Devices (PND)
• Portable Media Player (PMP)
• Mobile Handsets
• Communication
• Portable Computing
• Advanced DSP algorithms
3 Description
The TLV320AIC3254 (sometimes referred to as the
AIC3254) is a flexible, low-power, low-voltage stereo
audio codec with programmable inputs and outputs,
PowerTune capabilities, fully-programmable miniDSP,
fixed predefined and parameterizable signal
processing blocks, integrated PLL, integrated LDOs
and flexible digital interfaces.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TLV320AIC3254
VQFN (32)
5.00 mm x 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Block Diagram
IN1_L
IN2_L
IN3_L
IN3_R
IN2_R
IN1_R
SPI_Select
Reset
MicBias
Ref
Mic
Bias
Ref
AGC
+
0…+47.5 dB
Left
ADC
tpl
´
ADC
Signal
Proc.
+
Gain Adj.
0.5 dB
steps
-30...0 dB
DRC
Vol . Ctrl
-72...0dB
DAC
Signal
Proc.
´
Left
DAC
-6...+29dB
+
HPL
1dB steps
-6...+29dB
+
LOL
-30...0 dB
miniDSP
Data
Interface
miniDSP
1dB steps
-6...+29dB
+
LOR
0…
+
+47.5 dB
Right
ADC
Gain Adj.
ADC
´ tpr
Signal
Proc.
+
0.5 dB steps
AGC
DAC
Signal
Proc.
´
Right
DAC
1dB steps
-6...+29dB
+
HPR
DRC
Vol . Ctrl
-72...0dB
1dB steps
HPVdd
ALDO
DLDO
SPI / I2C
Control Block
PLL
Digital Interrupt Secondary Primary
Mic. Ctrl
I2S IF
I2S Interface
Supplies
Pin Muxing/ Clock Routing
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.