TLV320AIC3254-Q1 Datasheet, PDF (1/47 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec With Embedded miniDSP

TLV320AIC3254-Q1
www.ti.com
SLAS894A – MAY 2013 – REVISED AUGUST 2013
Ultra Low Power Stereo Audio Codec With Embedded miniDSP
Check for Samples: TLV320AIC3254-Q1
FEATURES
1
•2 Qualified for Automotive Applications
• AEC-Q100 Qualified with the Following
Results:
– Device Temperature Grade 3: –40°C to 85°C
Ambient Operating Temperature Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
• Stereo Audio DAC with 100dB SNR
• 4.1mW Stereo 48ksps DAC Playback
• Stereo Audio ADC with 93dB SNR
• 6.1mW Stereo 48ksps ADC Record
• PowerTune™
• Extensive Signal Processing Options
• Embedded miniDSP
• Six Single-Ended or Three Fully-Differential
Analog Inputs
• Stereo Analog and Digital Microphone Inputs
• Stereo Headphone Outputs
• Stereo Line Outputs
• Very Low-Noise PGA
• Low Power Analog Bypass Mode
• Programmable Microphone Bias
• Programmable PLL
• Integrated LDO
• 5 mm x 5 mm 32-pin QFN Package
APPLICATIONS
• Automotive
• Portable Navigation Devices (PND)
• Portable Media Player (PMP)
• Mobile Handsets
• Communication
• Portable Computing
• Acoustic Echo Cancellation (AEC)
• Active Noise Cancellation (ANC)
• Advanced DSP algorithms
DESCRIPTION
The TLV320AIC3254-Q1 (also called the AIC3254-
Q1) is a flexible, low-power, low-voltage stereo audio
codec with programmable inputs and outputs,
PowerTune capabilities, fully-programmable miniDSP,
fixed predefined and parameterizable signal
processing blocks, integrated PLL, integrated LDOs
and flexible digital interfaces.
IN1_L
IN2_L
IN3_L
IN3_R
IN2_R
IN1_R
SPI_Select
Reset
MicBias
Ref
Mic
Bias
Ref
AGC
+
0…+47.5 dB
Left
ADC
tpl
´
ADC
Signal
Proc.
+
Gain Adj.
0.5 dB
steps
-30...0 dB
DRC
Vol . Ctrl
-72...0dB
DAC
Signal
Proc.
´
Left
DAC
-6...+29dB
+
HPL
1dB steps
-6...+29dB
+
LOL
-30...0 dB
miniDSP
Data
Interface
miniDSP
1dB steps
-6...+29dB
+
LOR
0…
+
+47.5 dB
Right
ADC
Gain Adj.
ADC
´ tpr
Signal
Proc.
+
0.5 dB steps
AGC
DAC
Signal
Proc.
´
Right
DAC
1dB steps
-6...+29dB
+
HPR
DRC
Vol . Ctrl
-72...0dB
1dB steps
HPVdd
ALDO
DLDO
SPI / I2C
Control Block
PLL
Digital Interrupt Secondary Primary
Mic. Ctrl
I²S IF
I²S Interface
Supplies
Pin Muxing/ Clock Routing
Figure 1. Simplified Block Diagram
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerTune is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated