English
Language : 

TLV320AIC3206_17 Datasheet, PDF (1/51 Pages) Texas Instruments – Ultra Low-Power Stereo Audio Codec
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TLV320AIC3206
SLAS649C – DECEMBER 2010 – REVISED NOVEMBER 2014
TLV320AIC3206 Ultra Low-Power Stereo Audio Codec
1 Features
•1 Stereo Audio DAC with 100-dB SNR
• 5.8-mW Stereo 48-ksps DAC-to-Ground-Centered
Headphone Playback
• Stereo Audio ADC with 93-dB SNR
• 5.2-mW Stereo 48-ksps ADC Record
• PowerTune™
• Extensive Signal Processing Options
• Six Single-Ended or 3 Fully-Differential Analog
Inputs
• Stereo Analog and Digital Microphone Inputs
• Ground-Centered Stereo Headphone Outputs
• Very Low-Noise PGA
• Low Power Analog Bypass Mode
• Programmable Microphone Bias
• Programmable PLL
• 5-mm x 5-mm 40-pin QFN or 3.5-mm x 3.3-mm
42-ball WCSP (DSBGA) Package
2 Applications
• Portable Navigation Devices (PND)
• Portable Media Player (PMP)
• Mobile Handsets
• Communication
• Portable Computing
3 Description
The TLV320AIC3206 (sometimes referred to as the
AIC3206) is a flexible, low-power, low-voltage stereo
audio codec with programmable inputs and outputs,
PowerTune capabilities, fixed predefined and
parameterizable signal processing blocks, integrated
PLL and flexible digital interfaces.
Device Information(1)
PART NUMBER PACKAGE
BODY SIZE (NOM)
TLV320AIC3206
WQFN (40)
DSBGA (42)
5.00 mm x 5.00 mm
3.49 mm x 3.29 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Block Diagram
IN1_L
IN2_L
IN3_L
IN3_R
IN2_R
IN1_R
SPI_Select
Reset
MicBias
MicDet
Ref
Mic
Bias
Ref
AGC
+
0…+47.5 dB
Left
ADC
tpl
*
ADC
Signal
Proc.
+
Gain Adj.
0.5 dB
steps
-30...0 dB
DRC
Vol . Ctrl
DAC
Signal
Proc.
*
Left
DAC
-30...0 dB
Data Interface
0…
+
+47.5 dB
Right
ADC
Gain Adj.
ADC
* tpr
Signal
Proc.
+
0.5 dB steps
AGC
DAC
Signal
Proc.
DRC
* Right
DAC
Vol . Ctrl
-6...+14dB
+
HPL
1dB steps
-6...+29dB
+
LOL
1dB steps
-6...+29dB
+
LOR
1dB steps
-6...+14dB
+
HPR
1dB steps
GND_Sense
Supplies
SPI / I2C
Control Block
PLL
Dig
Mic
Inter
rupt
Sec.
I2S I/F
Primary
I2S Interface
Pin Muxing / Clock Routing
Charge
Pump
VNEG
Fly_N
Fly_P
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.