TLC1550I_15 Datasheet, PDF (1/18 Pages) Texas Instruments – 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS

TLC1550I, TLC1550M, TLC1551I
10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043G − MAY 1991 − REVISED NOVEMBER 2003
D Power Dissipation . . . 40 mW Max
D Advanced LinEPIC Single-Poly Process
Provides Close Capacitor Matching for
Better Accuracy
D Fast Parallel Processing for DSP and µP
Interface
D Either External or Internal Clock Can Be
Used
D Conversion Time . . . 6 µs
D Total Unadjusted Error . . . ±1 LSB Max
D CMOS Technology
description
The TLC1550x and TLC1551 are data acquisition
analog-to-digital converters (ADCs) using a 10-bit,
switched-capacitor, successive-approximation net-
work. A high-speed, 3-state parallel port directly
interfaces to a digital signal processor (DSP) or
microprocessor (µP) system data bus. D0 through
D9 are the digital output terminals with D0 being
the least significant bit (LSB). Separate power
terminals for the analog and digital portions
minimize noise pickup in the supply leads.
Additionally, the digital power is divided into two
parts to separate the lower current logic from the
higher current bus drivers. An external clock can be
applied to CLKIN to override the internal system
clock if desired.
The TLC1550I and TLC1551I are characterized for
operation from − 40°C to 85°C. The TLC1550M is
characterized over the full military range of − 55°C
to 125°C.
J† OR DW PACKAGE
(TOP VIEW)
REF+ ₁
REF − ₂
ANLG GND ₃
AIN ₄
ANLG V_{DD 5}
DGTL GND1 ₆
DGTL GND2 7
DGTL V_DD1 8
DGTL V_DD2 9
EOC 10
D0 11
D1 12
24 ^RD
23 ^WR
22 ^CLKIN
21 ^CS
20 ^D9
19 ^D8
18 D7
17 D6
16 D5
15 D4
14 D3
13 D2
† _{Refer to the mechanical data for the JW}
package.
FK OR FN PACKAGE
(TOP VIEW)
AIN
ANLG V_DD
DGTL GND1
NC
DGTL GND2
DGTL V_DD1
DGTL V_DD2
4 3 2 1 28 27 26
5
25 CS
6
24 D9
7
23 D8
8
22 NC
9
21 D7
10
20 D6
11
19 D5
12 13 14 15 16 17 18
NC − No internal connection
TA
CERAMIC CHIP CARRIER
(FK)
−40°C to 85°C
—
−55°C to 125°C
TLC1550MFK
AVAILABLE OPTIONS
PACKAGE
PLASTIC CHIP CARRIER
(FN)
TLC1550IFN
TLC1551IFN
—
CERAMIC DIP
(J)
—
TLC1550MJ
SOIC
(DW)
TLC1550IDW
TLC1551IDW
—
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinEPIC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1