TB5T1_14 Datasheet, PDF (1/22 Pages) Texas Instruments – DUAL DIFFERENTIAL PECL DRIVER/RECEIVER

www.ti.com
TB5T1
SLLS589C – NOVEMBER 2003 – REVISED OCTOBER 2007
DUAL DIFFERENTIAL PECL DRIVER/RECEIVER
FEATURES
1
• Functional Replacement for the Agere BTF1A
• Driver Features
– Third-State Logic Low Output
– ESD Protection HBM > 3 kV, CDM > 2 kV
– No Line Loading when V_CC = 0
– Capable of Driving 50-Ω loads
– 2.0-ns Maximum Propagation Delay
– 0.2-ns Output Skew (typical)
• Receiver Features
– High-Input Impedance Approximately 8 kΩ
– 4.0-ns Maximum Propagation Delay
– 50-mV Hysteresis
– Slew Rate Limited (1 ns min 80% to 20%)
– ESD Protection HBM > 3 kV, CDM > 2 kV
– -1.1-V to 7.1-V Input Voltage Range
• Common Device Features
– Common Enable for Each Driver/Receiver
Pair
– Operating Temperature Range: -40°C to
85°C
– Single 5.0 V ± 10% Supply
– Available in Gull-Wing SOIC (JEDEC
MS-013, DW) and SOIC (D) Package
DESCRIPTION
The TB5T1 device is a dual differential driver/receiver
circuit that transmits and receives digital data over
balanced transmission lines. The dual drivers
translate input TTL logic levels to differential
pseudo-ECL output levels. The dual receivers convert
differential-input logic levels to TTL output levels.
Each driver or receiver pair has its own common
enable control allowing serial data and a control clock
to be transmitted and received on a single integrated
circuit. The TB5T1 requires the customer to supply
termination resistors on the circuit board.
The power-down loading characteristics of the
receiver input circuit are approximately 8 kΩ relative
to the power supplies; hence, it does not load the
transmission line when the circuit is powered down.
In circuits with termination resistors, the line remains
impedance- matched when the circuit is powered
down. The driver does not load the line when it is
powered down.
All devices are characterized for operation from -40°C
to 85°C.
The logic inputs of this device include internal pull-up
resistors of approximately 40 kΩ that are connected
to V_CC to ensure a logical high level input if the inputs
are open circuited.
RO1
DI1
VCC
ED
ER
GND
DI2
RO2
PIN ASSIGNMENTS
DW AND D PACKAGE
(TOP VIEW)
1
16
RI1
2
15
RI1
3
14
DO1
4
13
DO1
5
12
DO2
6
11
DO2
7
10
RI2
8
9
RI2
FUNCTIONAL BLOCK DIAGRAM
DO1
DI1
DO1
DO2
DI2
DO2
ED
RI1
RO1
RI1
RI2
RO2
RI2
ER
Enable Truth Table
ED
ER
D1
D2
R1
R2
0
0
Active Active Active Active
1
0
Disabled Disabled Active Active
0
1
Active Active Disabled Disabled
1
1
Disabled Disabled Disabled Disabled
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated