TB5R1_17 Datasheet, PDF (1/16 Pages) Texas Instruments – QUAD DIFFERENTIAL PECL RECEIVERS

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TB5R1, TB5R2
SLLS588C – NOVEMBER 2003 – REVISED JANUARY 2008
QUAD DIFFERENTIAL PECL RECEIVERS
FEATURES
1
• Functional Replacements for the Agere
BRF1A, BRF2A, BRS2A, and BRS2B
• Pin Equivalent to General Trade 26LS32
• High Input Impedance Approximately 8 kΩ
• 4-ns Maximum Propagation Delay
• TB5R1 Provides 50-mV Hysteresis
• TB5R2 With -125-mV Threshold Offset for
Preferred State Output
• -1.1-V to 7.1-V Common Mode Range
• Single 5-V 10% Supply
• Slew Rate Limited (1 ns min 80% to 20%)
• TB5R2 Output Defaults to Logic 1 When Inputs
Left Open or Shorted to V_CC or GND
• ESD Protection HBM > 3 kV, CDM > 2 kV
• Operating Temperature Range: -40C to 85C
• Available in Gull-Wing SOIC (JEDEC MS-013,
DW) and SOIC (D) Package
APPLICATIONS
• Digital Data or Clock Transmission Over
Balanced Lines
DESCRIPTION
These quad differential receivers accept digital data
over balanced transmission lines. They translate
differential input logic levels to TTL output logic
levels.
The TB5R1 is a pin- and function-compatible
replacement for the Agere systems BRF1A and
BRF2A; it includes 3-kV HBM and 2-kV CDM ESD
protection.
The TB5R2 is a pin- and function-compatible
replacement for the Agere systems BRS2A and
BRS2B and incorporates a 125-mV receiver input
offset, preferred state output, 3-kV HBM and 2-kV
CDM ESD protection. The TB5R2 preferred state
feature places the high state when the inputs are
open, shorted to ground, or shorted to the power
supply.
The power-down loading characteristics of the
receiver input circuit are approximately 8 kΩ relative
to the power supplies; hence they do not load the
transmission line when the circuit is powered down.
The packaging for these differential line receivers
include a 16-pin gull wing SOIC (DW) and SOIC (D).
The enable inputs of this device include internal
pullup resistors of approximately 40 kΩ that are
connected to V_CC to ensure a logical high level input
if the inputs are open circuited.
PIN ASSIGNMENTS
D PACKAGE
(TOP VIEW)
AI
1
AI
2
AO
3
E1
4
BO
5
BI
6
BI
7
GND
8
16
VCC
15
DI
14
DI
13
DO
12
E2
11
CO
10
CI
9
CI
FUNCTIONAL BLOCK DIAGRAM
AI
AO
AI
BI
BI
BO
C1
CO
C1
D1
D1
DO
E1
E2
Enable Truth Table
E1
E2
CONDITION
0
0
Active
1
0
Active
0
1
Disabled
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2008, Texas Instruments Incorporated