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TAS2505-Q1 Datasheet, PDF (1/35 Pages) Texas Instruments – 2.6-W Digital/Analog Input Automotive Class-D Speaker Amplifier With Audio Processing
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TAS2505-Q1
SLASEI9 – JUNE 2017
TAS2505-Q1 2.6-W Digital/Analog Input Automotive Class-D Speaker Amplifier With Audio
Processing
1 Features
•1 Mono Class-D BTL Speaker Amplifier
– 2.6 W at 10% THD_N (4Ω, 5.5 V)
– 1.7 W at 10% THD+N (8 Ω, 5.5 V)
• Supports both Digital and Analog Input
• Single Supply 2.7 V to 5.5 V
• Load Diagnostic Functions:
– Output-to-GND Short
– Terminal-to-Terminal Short
– Output-to-Power Short
– Over Temperature
• Supports 9-kHz to 96-kHz Sample Rates
• Two Single-Ended Inputs with Output Mixing and
Level Control
• Embedded Power-On-Reset
• Programmable Digital Audio Processing:
– Bass Boost
– Treble
– EQ (up to 6 Biquads)
• I2S, Left-Justified, Right-Justified, DSP, and TDM
Audio Interfaces
• I2C and SPI Control With Auto-Increment
• 24-Pin, VQFN Package
2 Applications
• Instrument Cluster
• Automotive Emergency Call (eCall)
• Telematics
3 Description
The TAS2505-Q1 is a mono Class-D speaker amp
that supports both Digital and Analog inputs. The
device is ideal for automotive instrument cluster,
emergency call (eCall), and telematics applications.
Direct I2S input removes the need for an external
DAC in the audio signal path, and the integrated LDO
enables single supply operation. In addition to
integration, the device features programmable audio
processing. The onboard DSP supports bass boost,
treble, and EQ (up to 6 biquads). An on-chip PLL
provides the high-speed clock needed by the DSP.
The volume level is register controlled.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TAS2505
VQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Block Diagram
AINR
AINL
0 dB to -78 dB and Mute
(Min 0.5 dB steps)
DAC Signal
Proc.
Dig
Mono 6
Vol
' DAC
0 dB to -78 dB
and Mute
(Min 0.5 dB steps)
6
6 dB to +24 dB
(6 dB steps)
SPKP
SPKM
POR
LDO
SPI_SEL
RST
SPI/I2C
Control Block
Secondary I2S
Interface
Primary I2S
Interface
PLL
Interrupt
Control
Pin Muxing / Clock Routing
LDO_SEL
SPKVDD
AVDD
DVDD
IOVDD
SPKVSS
AVSS
DVSS
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.