SN75LVDS86_08 Datasheet, PDF (1/17 Pages) Texas Instruments – FLATLINK RECEIVER

SN75LVDS86
FlatLink RECEIVER
SLLS268D − MARCH 1997 − REVISED JULY 2006
D 3:21 Data Channel Expansion at up to
178.5 Mbytes/s Throughput
D Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
D Three Data Channels and Clock
Low-Voltage Differential Channels In and
21 Data and Clock Low-Voltage TTL
Channels Out
D Operates From a Single 3.3-V Supply and
250 mW (Typ)
D 5-V Tolerant SHTDN Input
D ESD Protection Exceeds 4 kV on Bus Pins
D Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal
Pitch
D Consumes Less Than 1 mW When Disabled
D Wide Phase-Lock Input Frequency Range
31 MHz to 68 MHz
D No External Components Required for PLL
D Open-Circuit Receiver Fail-Safe Design
D Inputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
D Improved Replacement for the Nationalt
DS90C562
DGG PACKAGE
(TOP VIEW)
D17 ₁
D18 ₂
GND ₃
D19 4
D20 5
NC 6
LVDSGND 7
A0M 8
A0P 9
A1M 10
A1P 11
LVDSV_CC 12
LVDSGND 13
A2M 14
A2P 15
CLKINM 16
CLKINP 17
LVDSGND 18
PLLGND 19
PLLV_CC 20
PLLGND 21
SHTDN 22
CLKOUT ²³
D0 ²⁴
48 ^V_CC
47 ^D16
46 ^D15
45 D14
44 GND
43 D13
42 V_CC
41 D12
40 D11
39 D10
38 GND
37 D9
36 V_CC
35 D8
34 D7
33 D6
32 GND
31 D5
30 D4
29 D3
28 V_CC
27 D2
26 _D1
25 _GND
description
NC − Not Connected
The SN75LVDS86 FlatLink receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock
synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These
functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84,
or ’85, over four balanced-pair conductors, and expansion to 21 bits of single-ended low-voltage TTL (LVTTL)
synchronous data at a lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at seven times (7×) the LVDS
input clock (CLKIN) rate. The data is then unloaded to a 21-bit-wide LVTTL parallel bus at the CLKIN rate. A
phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock
for the expanded data. The SN75LVDS86 presents valid data on the falling edge of the output clock (CLKOUT).
The SN75LVDS86 requires only four line-termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A
low level on this signal clears all internal registers to a low level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2006, Texas Instruments Incorporated
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