SN75LVDS82_15 Datasheet, PDF (1/20 Pages) Texas Instruments – FlatLink RECEIVER

SN75LVDS82
www.ti.com
FlatLink™ RECEIVER
Check for Samples: SN75LVDS82
SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011
FEATURES
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•23 4:28 Data Channel Expansion at up to
238 Mbytes/s Throughput
• Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
• Four Data Channels and Clock Low-Voltage
Differential Channels In and 28 Data and
Clock Low-Voltage TTL Channels Out
• Operates From a Single 3.3-V Supply With
250 mW (Typ)
• 5-V Tolerant SHTDN Input
• Falling Clock-Edge-Triggered Outputs
• Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal Pitch
• Consumes Less Than 1 mW When Disabled
• Wide Phase-Lock Input Frequency
Range . . . 31 MHz to 68 MHz
• No External Components Required for PLL
• Inputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
• Improved Replacement for the
National™ DS90C582
DESCRIPTION
The SN75LVDS82 FlatLink™ receiver contains four
serial-in, 7-bit parallel-out shift registers, a 7× clock
synthesizer, and five low-voltage differential signaling
(LVDS) line receivers in a single integrated circuit.
DGG PACKAGE
(TOP VIEW)
D22 ₁
D23 2
D24 3
GND 4
D25 5
D26 6
D27 7
LVDSGND 8
A0M 9
A0P 10
A1M 11
A1P 12
LVDSV_CC 13
LVDSGND 14
A2M 15
A2P 16
CLKINM 17
CLKINP 18
A3M 19
A3P 20
LVDSGND 21
PLLGND 22
PLLV_CC ²³
PLLGND ²⁴
SHTDN ²⁵
CLKOUT ²⁶
D0 ²⁷
GND ²⁸
56 ^VCC
55 D21
54 D20
53 D19
52 GND
51 D18
50 D17
49 D16
48 V_CC
47 D15
46 D14
45 D13
44 GND
43 D12
42 D11
41 D10
40 V_CC
39 D9
38 D8
37 D7
36 GND
35 D6
34 _D5
33 _D4
32 _D3
31 _VCC
30 _D2
29 _D1
These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81,
over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL)
synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 or
SN75LVDS85 for 21-bit transfers.
When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×)
the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate.
A phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock
for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a trademark of Texas Instruments.
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All other trademarks are the property of their respective owners.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1996–2011, Texas Instruments Incorporated