SN75LVDM976_08 Datasheet, PDF (1/30 Pages) Texas Instruments – 9-CHANNEL DUAL-MODE TRANSCEIVERS

www.ti.com
SN75LVDM976
SN75LVDM977
SLLS292B – APRIL 1998 – REVISED JANUARY 2000
9-CHANNEL DUAL-MODE TRANSCEIVERS
FEATURES
• 9 Channels for the Data and Control Paths of
the Small Computer Systems Interface (SCSI)
• Supports Single-Ended and Low-Voltage
Differential (LVD) SCSI
• CMOS Input Levels ('LVDM976) or TTL Input
Levels ('LVDM977) Available
• Includes DIFFSENS Comparators on CDE0
• Single-Ended Receivers Include Noise Pulse
Rejection Circuitry
• Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
• Low Disabled Supply Current 7 mA Maximum
• Power-Up/Down Glitch Protection
• Bus is High-Impedance With V_CC = 1.5 V
• Pin-Compatible With the SN75976ADGG
High-Voltage Differential Transceiver
DESCRIPTION
The SN75LVDM976 and SN75LVDM977 have nine
transceivers for transmitting or receiving the signals
to or from a SCSI data bus. They offer electrical
compatibility to both the single-ended signaling of
X3.277:1996-SCSI-3 Parallel Interface (Fast-20) and
the new low-voltage differential signaling method of
proposed standard 1142-D SCSI Parallel Interface –
2 (SPI-2).
The differential drivers are nonsymmetrical. The SCSI
bus uses a dc bias on the line to allow terminated fail
safe and wired-OR signaling. This bias can be as
high as 125 mV and induces a difference in the
high-to-low and low-to-high transition times of a
symmetrical driver. In order to reduce pulse skew, an
LVD SCSI driver's output characteristics become
nonsymmetrical. In other words, there is more
assertion current than negation current to or from the
driver. This allows the actual differential signal
voltage on the bus to be symmetrical about 0 V. Even
though the driver output characteristics are
nonsymmetrical, the design of the 'LVDM976 drivers
maintains balanced signaling. Balanced means that
the current that flows in each signal line is nearly
equal but opposite in direction and is one of the keys
to the low-noise performance of a differential bus.
DGG PACKAGE
(TOP VIEW)
INV/NON ₁
GND 2
GND 3
1A 4
1DE/RE 5
2A 6
2DE/RE 7
3A 8
3DE/RE 9
4A 10
4DE/RE 11
V_CC 12
GND 13
GND 14
GND 15
GND 16
GND 17
V_CC 18
5A 19
5DE/RE 20
6A 21
6DE/RE 22
7A ²³
7DE/RE ²⁴
8A ²⁵
8DE/RE ²⁶
9A ²⁷
9DE/RE ²⁸
56 ^CDE2
55 CDE1
54 CDE0
53 9B+
52 9B–
51 8B+
50 8B–
49 7B+
48 7B–
47 6B+
46 6B–
45 V_CC
44 GND
43 GND
42 GND
41 GND
40 GND
39 V_CC
38 5B+
37 5B–
36 4B+
35 4B–
34 _3B+
33 _3B–
32 _2B+
31 _2B–
30 _1B+
29 _1B–
T_A
0°C to
70°C
AVAILABLE OPTIONS
PACKAGE
TSSOP (DGG)
CMOS INPUT LEVELS
TSSOP (DGG)
TTL INPUTS
LEVELS
SN75LVDM976DGG
SN75LVDM977DGG
SN75LVDM976DGGR⁽¹⁾ SN75LVDM977DGGR⁽¹⁾
(1) The R suffix designates a taped and reeled package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2000, Texas Instruments Incorporated