SN74VMEH22501A-EP_15 Datasheet, PDF (1/38 Pages) Texas Instruments – 8-Bit Universal Bus Transceiver and Two 1-Bit Bus Transceivers

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SN74VMEH22501A-EP
SCES625A – FEBRUARY 2005 – REVISED NOVEMBER 2015
SN74VMEH22501A-EP 8-Bit Universal Bus Transceiver and Two 1-Bit Bus Transceivers
With Split LVTTL Port, Feedback Path, and 3-State Outputs
1 Features
•1 Controlled Baseline
– One Assembly/Test Site, One Fabrication Site
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree⁽¹⁾
• Member of the Texas Instruments Widebus™
Family
• UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, or Clocked Modes
• OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference (EMI)
• Compliant With VME64, 2eVME, and 2eSST
Protocols Validated at T_A = –40°C to 85°C
• Bus Transceiver Split LVTTL Port Provides a
Feedback Path for Control and Diagnostics
Monitoring
• I/O Interfaces are 5-V Tolerant
• B-Port Outputs (–48 mA/64 mA)
• Y and A-Port Outputs (–12 mA/12 mA)
• I_off, Power-Up 3-State, and BIAS V_CC Support Live
Insertion
• Bus Hold on 3A-Port Data Inputs
• 26-Ω Equivalent Series Resistor on 3A Ports and
Y Outputs
• Flow-Through Architecture Facilitates Printed
Circuit Board Layout
• Distributed V_CC and GND Pins Minimize High-
Speed Switching Noise
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
• Industrial Controls
• Telecommunications
• Instrumentation Systems
3 Description
The SN74VMEH22501A-EP 8-bit universal bus
transceiver has two integral 1-bit three-wire bus
transceivers and is designed for 3.3-V V_CC operation
with 5-V tolerant inputs. The UBT transceiver allows
transparent, latched, and flip-flop modes of data
transfer, and the separate LVTTL input and outputs
on the bus transceivers provide a feedback path for
control and diagnostics monitoring. This device
provides a high-speed interface between cards
operating at LVTTL logic levels and VME64, VME64x,
or VME320⁽²⁾ backplane topologies.
Device Information⁽³⁾
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74VMEH22501A-EP
TSSOP (48)
TVSOP (48)
4.40 mm × 9.70 mm
6.10 mm × 12.50 mm
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
(2) VME320 is a patented backplane construction by Arizona
Digital, Inc.
(3) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1OEAB 48
1OEBY 1
1A 2
1Y 3
2OEAB 41
2OEBY 8
2A 5
2Y 6
OE 14
46 _1B
43 _2B
DIR 24
CLKAB 32
LE 11
CLKBA 17
3A1 9
1D
40 _3B1
C1
CLK
1D
C1
CLK
To Seven Other Channels
Pin numbers shown for DGG and DGV
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.