SN74SSTV32852-EP Datasheet, PDF (1/10 Pages) Texas Instruments – 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS

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SN74SSTV32852-EP
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
SCES700 – OCTOBER 2007
FEATURES
1
•2 Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
• Extended Temperature Performance of –40°C
to 85°C
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree ⁽¹⁾
• Member of the Texas Instruments Widebus™
Family
• 1-to-2 Outputs Support Stacked DDR DIMMs
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
• Supports SSTL_2 Data Inputs
• Outputs Meet SSTL_2 Class II Specifications
• Differential Clock (CLK and CLK) Inputs
• Supports LVCMOS Switching Levels on the
RESET Input
• RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low
• Pinout Optimizes DIMM PCB Layout
• One Device Per DIMM Required
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V V_CC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.
The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing of
CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be
held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
T_A
–40°C to 85°C
ORDERING INFORMATION⁽¹⁾
PACKAGE ⁽²⁾
ORDERABLE PART NUMBER
LFBGA – GKF
Tape and reel
CSSTV32852GKFREP
TOP-SIDE MARKING
SV852IEP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated