SN74SSTUB32866_17 Datasheet, PDF (1/39 Pages) Texas Instruments – 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

SN74SSTUB32866
www.ti.com
SCAS792C – OCTOBER 2006 – REVISED NOVEMBER 2007
25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
FEATURES
1
•2 Member of the Texas Instruments Widebus+™
Family
• Pinout Optimizes DDR2 DIMM PCB Layout
• Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer
• Chip-Select Inputs Gate the Data Outputs from
Changing State and Minimizes System Power
Consumption
• Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
• Supports SSTL_18 Data Inputs
• Differential Clock (CLK and CLK) Inputs
• Supports LVCMOS Switching Levels on the
Control and RESET Inputs
• Checks Parity on DIMM-Independent Data
Inputs
• Able to Cascade with a Second
SN74SSTUB32866
• Supports Industrial Temperature Range
(-40°C to 85°C)
DESCRIPTION
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the
1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the
open-drain error (QERR) output.
The SN74SSTUB32866 operates from a differential clock (CLK and CLK). Data are registered at the crossing of
CLK going high and CLK going low.
The SN74SSTUB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input,
compares it with the data received on the DIMM-independent D-inputs (D2–D3, D5–D6, D8–D25 when C0 = 0
and C1 = 0; D2–D3, D5–D6, D8–D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and
indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even
parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs,
combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known
logic state.
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the
PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the
data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.
When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied
high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it
applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered,
the corresponding PPO and QERR signals are generated on the second device. The PPO output of the first
register is cascaded to the PAR_IN of the second SN74SSTUB32866. The QERR output of the first
SN74SSTUB32866 is left floating, and the valid error information is latched on the QERR output of the second
SN74SSTUB32866.
T_A
-40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
LFBGA–ZKE
Tape and reel
SN74SSTUB32866ZKER
LFBGA–ZWL
Tape and reel
SN74SSTUB32866ZWLR
TOP-SIDE MARKING
SB866
SB866
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated