SN74LVTH543-EP Datasheet, PDF (1/10 Pages) Texas Instruments – 3.3-V ABT OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

SN74LVTH543ĆEP
3.3ĆV ABT OCTAL REGISTERED TRANSCEIVER
WITH 3ĆSTATE OUTPUTS
SCBS772 − NOVEMBER 2003
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V_CC )
D Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
D Supports Unregulated Battery Operation
Down to 2.7 V
D I_off and Power-Up 3-State Support Hot
Insertion
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
PW PACKAGE
(TOP VIEW)
LEBA 1
OEBA ²
A1 ³
A2 ⁴
A3 ⁵
A4 ⁶
A5 ⁷
A6 ⁸
A7 ⁹
A8 ¹⁰
CEAB ¹¹
GND ¹²
24 V_CC
23 _CEBA
22 _B1
21 _B2
20 _B3
19 _B4
18 _B5
17 _B6
16 _B7
15 _B8
14 _LEAB
13 _OEAB
description/ordering information
This octal transceiver is designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The SN74LVTH543 contains two sets of D-type latches for temporary storage of data flowing in either direction.
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each
register, to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA
inputs.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 85°C TSSOP − PW Tape and reel SN74LVTH543IPWREP LH543EP
‡ _{Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines}
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright  2003, Texas Instruments Incorporated
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