SN74LVT8996-EP Datasheet, PDF (1/42 Pages) Texas Instruments – 3.3-V 10-BIT ADDRESSABLE SCAN PORT MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (KTAG) TAP TRANSCEIVER

SN74LVT8996ĆEP
3.3ĆV 10ĆBIT ADDRESSABLE SCAN PORT
MULTIDROPĆADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVER
SCBS764 − SEPTEMBER 2003
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D Member of the Texas Instruments (TI )
Broad Family of Testability Products
Supporting IEEE Std 1149.1-1990 (JTAG)
Test Access Port (TAP) and Boundary-Scan
Architecture
D Extends Scan Access From Board Level to
Higher Levels of System Integration
D Promotes Reuse of Lower-Level
(Chip/Board) Tests in System Environment
D While Powered at 3.3 V, Both the Primary
and Secondary TAPs Are Fully 5-V Tolerant
for Interfacing to 5-V and/or 3.3-V Masters
and Targets
D Switch-Based Architecture Allows Direct
Connect of Primary TAP to Secondary TAP
D Primary TAP Is Multidrop for Minimal Use of
Backplane Wiring Channels
D Shadow Protocols Can Occur in Any of
Test-Logic-Reset, Run-Test/Idle, Pause-DR,
and Pause-IR TAP States to Provide for
Board-to-Board Test and Built-In Self-Test
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D Simple Addressing (Shadow) Protocol Is
Received/Acknowledged on Primary TAP
D 10-Bit Address Space Provides for up to
1021 User-Specified Board Addresses
D Bypass (BYP) Pin Forces
Primary-to-Secondary Connection Without
Use of Shadow Protocols
D Connect (CON) Pin Provides Indication of
Primary-to-Secondary Connection
D High-Drive Outputs (−32-mA I_OH, 64-mA I_OL)
Support Backplane Interface at Primary and
High Fanout at Secondary
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
A4 1
A3 2
A2 3
A1 4
A0 5
BYP 6
GND 7
PTDO 8
PTCK 9
PTMS 10
PTDI 11
PTRST 12
24 A5
23 A6
22 A7
21 A8
20 A9
19 V_CC
18 CON
17 STDI
16 STCK
15 STMS
14 STDO
13 STRST
description/ordering information
The SN74LVT8996 10-bit addressable scan port (ASP) is a member of the Texas Instruments SCOPE testability
integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing
of complex circuit assemblies. Unlike most SCOPE devices, the ASP is not a boundary-scannable device, rather,
it applies TI’s addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to
extend scan access beyond the board level.
This device is functionally equivalent to the ’ABT8996 ASPs. Additionally, it is designed specifically for low-voltage
(3.3-V) V_CC operation, but with the capability to interface to 5-V masters and/or targets.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2003, Texas Instruments Incorporated
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