SN74LVT8980A-EP Datasheet, PDF (1/37 Pages) Texas Instruments – EMBEDDED TEST-BUS CONTROLLER IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8-BIT GENERIC HOST INTERFACES

SN74LVT8980AĆEP
EMBEDDED TESTĆBUS CONTROLLER
IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 8ĆBIT GENERIC HOST INTERFACES
SCBS761A − JUNE 2003 − REVISED OCTOBER 2003
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D Member of Texas Instruments Broad Family
of Testability Products Supporting IEEE Std
1149.1-1990 (JTAG) Test Access Port (TAP)
and Boundary-Scan Architecture
D Provide Built-In Access to IEEE Std 1149.1
Scan-Accessible Test/Maintenance
Facilities at Board and System Levels
D While Powered at 3.3 V, the TAP Interface Is
Fully 5-V Tolerant for Mastering Both 5-V
and/or 3.3-V IEEE Std 1149.1 Targets
D Simple Interface to Low-Cost 3.3-V
Microprocessors/Microcontrollers Via 8-Bit
Asynchronous Read/Write Data Bus
D Easy Programming Via Scan-Level
Command Set and Smart TAP Control
D Transparently Generate Protocols to
Support Multidrop TAP Configurations
Using TI’s Addressable Scan Port
† _{Component qualification in accordance with JEDEC and industry}
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
D Flexible TCK Generator Provides
Programmable Division, Gated-TCK, and
Free-Running-TCK Modes
D Discrete TAP Control Mode Supports
Arbitrary TMS/TDI Sequences for
Noncompliant Targets
D Programmable 32-Bit Test Cycle Counter
Allows Virtually Unlimited Scan/Test Length
D Accommodates Target Retiming (Pipeline)
Delays of Up To 15 TCK Cycles
D Test Output Enable (TOE) Allows for
External Control of TAP Signals
D High-Drive Outputs (−32-mA I_OH, 64-mA I_OL)
at TAP Support Backplane Interface and/or
High Fanout
DW PACKAGE
(TOP VIEW)
STRB 1
R/W 2
D0 3
D1 4
D2 5
D3 6
GND 7
D4 8
D5 9
D6 10
D7 11
CLKIN 12
24 A0
23 A1
22 A2
21 RDY
20 TDO
19 V_CC
18 TCK
17 TMS
16 TRST
15 TDI
14 RST
13 TOE
description/ordering information
The SN74LVT8980A embedded test-bus controllers (eTBCs) are members of the TI broad family of testability
integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of
complex circuit assemblies. Unlike most other devices of this family, the eTBCs are not boundary-scannable
devices; rather, their function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command
of an embedded host microprocessor/microcontroller. Thus, the eTBCs enable the practical and effective use
of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and
configuration/maintenance facilities at board and system levels.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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Copyright  2003, Texas Instruments Incorporated
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