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SN74LVT125-Q1 Datasheet, PDF (1/10 Pages) Texas Instruments – 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS
SN74LVT125-Q1
www.ti.com....................................................................................................................................................... SCBS763B – AUGUST 2003 – REVISED APRIL 2008
3.3-V ABT QUADRUPLE BUS BUFFER
WITH 3-STATE OUTPUTS
FEATURES
1
• Qualified for Automotive Applications
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
• Supports Unregulated Battery Operation Down
to 2.7 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Partial-Power-Down Mode
Operation
• Bus-Hold Data Inputs Eliminate the Need for
External Pullup Resistors
D OR PW PACKAGE
(TOP VIEW)
1OE 1
1A 2
1Y 3
2OE 4
2A 5
2Y 6
GND 7
14 VCC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
DESCRIPTION/ORDERING INFORMATION
This bus buffer is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a
TTL interface to a 5-V system environment.
The SN74LVT125-Q1 features independent line drivers with 3-state outputs. Each output is in the
high-impedance state when the associated output-enable (OE) input is high.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
TA
–40°C to 125°C
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
SOIC – D
Tape and reel
SN74LVT125QDRQ1
TSSOP – PW
Tape and reel
SN74LVT125QPWRQ1
TOP-SIDE MARKING
LVT125Q
LVT125Q
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2008, Texas Instruments Incorporated
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