SN74LVT125-EP Datasheet, PDF (1/11 Pages) Texas Instruments – 3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS

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FEATURES
• Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
• Extended Temperature Performance of
–40°C to 125°C
• Enhanced Diminishing Manufacturing
Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree⁽¹⁾
• ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
• Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V_CC)
(1) _{Component qualification in accordance with JEDEC and}
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LVT125-EP
3.3-V ABT QUADRUPLE BUS BUFFER
WITH 3-STATE OUTPUTS
SCBS796A – JANUARY 2004 – REVISED JUNE 2005
• Supports Unregulated Battery Operation
Down to 2.7 V
• Typical V_OLP (Output Ground Bounce) < 0.8 V
at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Partial-Power-Down Mode
Operation
• Bus-Hold Data Inputs Eliminate the Need for
External Pullup Resistors
D OR PW PACKAGE
(TOP VIEW)
1OE ¹
1A ²
1Y ³
2OE ⁴
2A ⁵
2Y ⁶
GND ⁷
14 V_CC
13 4OE
12 4A
11 4Y
10 3OE
9 3A
8 3Y
DESCRIPTION/ORDERING INFORMATION
This bus buffer is designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a
TTL interface to a 5-V system environment.
The SN74LVT125 features independent line drivers with 3-state outputs. Each output is in the high-impedance
state when the associated output-enable (OE) input is high.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
T_A
–40°C to 125°C
SOIC – D
TSSOP – PW
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
Tape and reel
SN74LVT125QDREP
Tape and reel
SN74LVT125QPWREP
TOP-SIDE MARKING
LVT125E
LVT125E
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2005, Texas Instruments Incorporated