SN74LVCH32374A_16 Datasheet, PDF (1/14 Pages) Texas Instruments – 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

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SN74LVCH32374A
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS619E – OCTOBER 1998 – REVISED AUGUST 2007
FEATURES
1
•2 Member of the Texas Instruments Widebus+™
Family
• Operates From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.5 ns at 3.3 V
• Typical V_OLP (Output Ground Bounce) < 0.8 V
at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V
at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Partial-Power-Down Mode
Operation
• Supports Mixed-Mode Signal Operation on All
Ports (5-V Input and Output Voltages With
3.3-V V_CC)
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
DESCRIPTION/ORDERING INFORMATION
This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.
The SN74LVCH32374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On
the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the
data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE ^{(1) (2)}
ORDERABLE PART NUMBER
LFBGA – GKE
LFBGA – ZKE (Pb-free)
SN74LVCH32374AGKER
Tape and reel
SN74LVCH32374AZKER
TOP-SIDE MARKING
CH374A
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2007, Texas Instruments Incorporated