SN74LVCH32373A_13 Datasheet, PDF (1/13 Pages) Texas Instruments – 32-BIT TRANSPARENT D-TYPE LATCH

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FEATURES
• Member of the Texas Instruments Widebus+™
Family
• Operates From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 4.2 ns at 3.3 V
• Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
• I_off Supports Partial-Power-Down Mode
Operation
SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS618D – OCTOBER 1998 – REVISED MARCH 2005
• Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V V_CC)
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V V_CC operation.
The SN74LVCH32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When
the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs
are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
T_A
–40°C to 85°C
PACKAGE ⁽¹⁾
LFBGA – GKE
Tape and reel
ORDERABLE PART NUMBER
SN74LVCH32373AGKER
TOP-SIDE MARKING
CH373A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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