SN74LVCH16901_14 Datasheet, PDF (1/13 Pages) Texas Instruments – 18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS

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Not Recommended For New Designs
SN74LVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES145C – OCTOBER 1998 – REVISED JUNE 2005
FEATURES
• Member of the Texas Instruments Widebus+™
Family
• UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, or Clocked Modes
• Operates From 1.65 V to 3.6 V
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 5.4 ns at 3.3 V
• Typical V_OLP (Output Ground Bounce) < 0.8 V
at V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) > 2 V at
V_CC = 3.3 V, T_A = 25°C
• Simultaneously Generates and Checks Parity
• Option to Select Generate Parity and Check or
Feedthrough Data/Parity in A-to-B or B-to-A
Direction
• Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V V_CC)
• I_off Supports Partial-Power-Down Mode
Operation
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class I
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DGG PACKAGE
(TOP VIEW)
1CLKENAB 1
LEAB 2
CLKAB 3
1ERRA 4
1APAR 5
GND 6
1A1 7
1A2 8
1A3 9
V_CC 10
1A4 11
1A5 12
1A6 13
GND 14
1A7 15
1A8 16
2A1 17
2A2 18
GND 19
2A3 20
2A4 21
2A5 22
V_CC 23
2A6 24
2A7 25
2A8 26
GND 27
2APAR 28
2ERRA 29
OEAB 30
SEL 31
2CLKENAB 32
64 1CLKENBA
63 LEBA
62 CLKBA
61 1ERRB
60 1BPAR
59 GND
58 1B1
57 1B2
56 1B3
55 V_CC
54 1B4
53 1B5
52 1B6
51 GND
50 1B7
49 1B8
48 2B1
47 2B2
46 GND
45 2B3
44 2B4
43 2B5
42 V_CC
41 2B6
40 2B7
39 2B8
38 GND
37 2BPAR
36 2ERRB
35 OEBA
34 ODD/EVEN
33 2CLKENBA
DESCRIPTION/ORDERING INFORMATION
This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V V_CC operation.
The SN74LVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a
feed-through transceiver, or it can generate/check parity from the two 8-bit data buses in either direction.
T_A
–40°C to 85°C
ORDERING INFORMATION
PACKAGE ⁽¹⁾
ORDERABLE PART NUMBER
TSSOP – DGG
Tape and reel
SN74LVCH16901DGGR
TOP-SIDE MARKING
LVCH16901
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, UBT are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2005, Texas Instruments Incorporated