SN74LVC74A-EP Datasheet, PDF (1/13 Pages) Texas Instruments – DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74LVC74A-EP
DUAL POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS751C – DECEMBER 2003 – REVISED SEPTEMBER 2007
FEATURES
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• Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
• Extended Temperature Performance of –40°C
to 125°C and –55°C to 125°C
• Enhanced Diminishing Manufacturing Sources
(DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree ⁽¹⁾
• Operates From 2 V to 3.6 V
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
• Inputs Accept Voltages to 5.5 V
• Max t_pd of 5.2 ns at 3.3 V
• Typical V_OLP (Output Ground Bounce) <0.8 V at
V_CC = 3.3 V, T_A = 25°C
• Typical V_OHV (Output V_OH Undershoot) >2 V at
V_CC = 3.3 V, T_A = 25°C
D OR PW PACKAGE
(TOP VIEW)
1CLR 1
1D 2
1CLK 3
1PRE 4
1Q 5
1Q 6
GND 7
14 V_CC
13 2CLR
12 2D
11 2CLK
10 2PRE
9 _2Q
8 _2Q
DESCRIPTION/ORDERING INFORMATION
The SN74LVC74A dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V_CC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as a translator in
a mixed 3.3 V/5 V system environment.
T_A
–40°C to 125°C
–55°C to 125°C
ORDERING INFORMATION⁽¹⁾
PACKAGE ⁽²⁾
ORDERABLE PART NUMBER
SOIC – D
Reel of 2500
SN74LVC74AQDREP
TSSOP – PW
Reel of 2000
SN74LVC74AQPWREP
SOIC – D
Reel of 2500
SN74LVC74AMDREP
TSSOP – PW
Reel of 2000
SN74LVC74AMPWREP
TOP-SIDE MARKING
LVC74AE
LVC74AE
LVC74AM
LVC74AM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated